Method and apparatus for providing thermal shutdown and current limiting protection
Granted: July 27, 2004
Patent Number:
6768622
The present invention provides an apparatus and method for preventing damage to a system due to runaway current and provides for the reactivation of the system. The shutdown and reactivation method and apparatus includes a driving circuit which supplies an output current to a load. If a runaway current condition occurs in the system the shutdown and reactivation apparatus is activated by triggering a shutdown signal which deactivates the driving circuit such that the output current is no…
Electrical field alignment vernier
Granted: July 13, 2004
Patent Number:
6762432
A test structure pattern includes a first comb having a first set of tines, and a second comb having a second set of tines of the same width and spacing as the first set of tines. When the test structure pattern is stepped between fields on a wafer, the first comb and the second comb at least partially overlap on photoresist over a scribe lane between the fields. When the photoresist is developed, the overlap of the first comb and the second comb generates a metal comb. Electrical…
Electrical print resolution test die
Granted: July 13, 2004
Patent Number:
6762434
A test structure pattern includes a first comb, a second comb, and a serpentine line. The first comb includes a first set of tines of the same orientation. The second comb includes a second set of tines of the same orientation that are interdigitated with the first set of tines. The serpentine line runs between the interdigitated tines of the first metal comb and the second metal comb. The test structure pattern forms a first metal comb, a second metal comb, and a serpentine metal line…
Switched capacitor peak detector with variable time constant asymmetrical filtering
Granted: July 13, 2004
Patent Number:
6762627
A peak detector employs switched capacitor filtering to implement long time constant and variable attack and decay characteristics. In one embodiment, the peak detector includes a first switch, a rectifier, a first capacitor and a second switch in the attack path, and a third switch, a second capacitor and a fourth switch in the decay path. The peak detector further includes a third capacitor coupled to the attack and decay paths and having a capacitance greater than the capacitance of…
Multi-technology complementary bipolar output using polysilicon emitter and buried power buss with low temperature processing
Granted: June 22, 2004
Patent Number:
6753592
A dual polysilicon emitter, complementary output is provided which utilizes a buried power buss. While providing these advantages, the process is not complicated. The process has the speed performance of the ASSET technology with an easier process to produce. In addition, the process described in the present invention provides additional advantages that the ASSET process does not have.
Amplifier circuit for adding a laplace transform zero in a linear integrated circuit
Granted: May 18, 2004
Patent Number:
6737841
A compensation circuit for introducing a zero in a first circuit being incorporated in a closed loop feedback system includes a first capacitor, an amplifier with capacitive feedback and a second capacitor, connected in series between an input node and a summing node in the first circuit. In one embodiment, the summing node is an intermediate node between two gain stages of a second circuit in the first circuit. The capacitive feedback can be formed by a third capacitor coupled in…
Bootstrap reference circuit including a shunt bandgap regulator with external start-up current source
Granted: May 18, 2004
Patent Number:
6737908
A bootstrap reference circuit includes a shunt regulator for generating a reference voltage at a first node, a current source generating a current, and a current mirror coupling the current to the shunt regulator for supplying the shunt regulator. In operation, when the shunt regulator is powering up, the current has an increasing magnitude when a voltage at the first node is less than a predefined voltage value where the predefined voltage value is less than the reference voltage.…
Voltage level-shifting control circuit for electronic switch
Granted: May 11, 2004
Patent Number:
6734704
A control circuit receives complementary logic signals ranging from Vdd to 0 VDC, and outputs a drive signal Vhs1 ranging from magnitude Vhv to Vhv+Vdd to control a high-side switch. The control circuit includes an Ibias generator and a level shift circuit that preferably includes a passive current sink mechanism, coupleable between Vdd and ground. The level shift circuit includes a totem-pole configuration of a PMOS device, an NMOS device, and an NMOS device that mirrors Ibias…
Error amplifier circuit
Granted: April 20, 2004
Patent Number:
6724257
An error amplifier circuit includes a differential amplifier with a cascode gain stage and an amplifier. The differential amplifier receives a first input signal and a second input signal and generates an output signal on an output terminal indicative of the difference between the first input signal and the second input signal. The cascode gain stage is coupled to receive the output signal of the differential amplifier and generates a second output signal. The cascode gain stage is…
Programmable optical array
Granted: March 23, 2004
Patent Number:
6711046
Programmable semiconductor elements, such as zener diodes, are used in an optical array. In one embodiment, an array of zener diodes is formed on a substrate surface and selectively zapped (programmed) to create a reflective filament between anode and cathode contacts of the selected zener diodes. Light is then applied to the surface. The reflected (or transmitted) light pattern may be used for conveying optical information or exposing a photoresist layer. In one use of the array to…
Method of fabricating a bipolar transistor using selective epitaxially grown SiGe base layer
Granted: March 2, 2004
Patent Number:
6699765
Embodiments of a bipolar transistor are disclosed, along with methods for making the transistor. An exemplary transistor includes a collector region in a semiconductor substrate, a base layer overlying the collector region and bound by a field oxide layer, a dielectric isolation layer overlying the base layer, and an emitter structure overlying the dielectric isolation layer and contacting the base layer through a central aperture in the dielectric layer. The transistor may be a…
ESD protection device for enhancing reliability and for providing control of ESD trigger voltage
Granted: February 24, 2004
Patent Number:
6696731
A diode-triggered NPN ESD protection device includes a P-Base region enclosing the emitter region of the NPN transistor for enhancing the reliability of the ESD protection device. The incorporation of the P-Base region encourages bulk transistor action and inhibits surface transistor action such that the reliability of the protection device is enhanced. In another aspect of the present invention, a trigger voltage control method is applied to a diode-triggered ESD protection device to…
Method and system for address lookup in data communication
Granted: February 10, 2004
Patent Number:
6691171
A system and method searches for a longest prefix match for an address having a number of binary bits among a plurality of entries having different lengths of bits. The entries are associated with a trie having a first number of trie nodes for L-bit trie match, wherein L is a predetermined integer greater than 1, and at least a first trie unit including at least one trie node for K1-bit trie match and at least one trie node for K2-bit trie match, wherein K1 and K2 are two different…
Fully integrated all-CMOS AM transmitter with automatic antenna tuning
Granted: February 3, 2004
Patent Number:
6687488
A monolithic AM transmitter is disclosed. An external antenna forms part of a resonance network so that the antenna resonance point is automatically tuned to the transmit frequency. This provides flexibility with no added cost to the transmitter.
Radio receiver in CMOS integrated circuit
Granted: December 9, 2003
Patent Number:
6662003
A single chip superhetrodyne AM receiver is disclosed herein. To compensate for process variations in the implementation of the IC, bias currents setting the operating conditions for various amplifiers and other components in the system are adjusted based on frequency control signals in a PLL circuit in the local oscillator. Since the magnitude of the control signal reflects the process variations, the bias currents are adjusted based on the control signal to offset these variations in…
Fully integrated ALL-CMOS AM transmitter with automatic antenna tuning
Granted: December 2, 2003
Patent Number:
6658239
A monolithic AM transmitter is disclosed. An external antenna forms part of a resonance network so that the antenna resonance point is automatically tuned to the transmit frequency. This provides flexibility with no added cost to the transmitter. Additionally, components of the transmitter can be formed on a single monolithic integrated circuit.
Electrical print resolution test die
Granted: November 18, 2003
Patent Number:
6649932
A test structure pattern includes a first comb, a second comb, and a serpentine line. The first comb includes a first set of tines of the same orientation. The second comb includes a second set of tines of the same orientation that are interdigitated with the first set of tines. The serpentine line runs between the interdigitated tines of the first metal comb and the second metal comb. The test structure pattern forms a first metal comb, a second metal comb, and a serpentine metal line…
Localized electrostatic discharge protection for integrated circuit input/output pads
Granted: November 18, 2003
Patent Number:
6650165
Systems and methods are disclosed for localized electrostatic discharge protection of integrated circuit input/output pads. The localized clamp is isolated from the main supply voltage clamp and coupled to the input/output pad through low-capacitance diodes.
Apparatus for converting voltage with regulator
Granted: November 11, 2003
Patent Number:
6646424
The present invention provides an apparatus and method for optimizing the efficiency of a switching converter for converting a first voltage to a second voltage. The apparatus includes a regulator, a DC-to-DC converter and a controller. The controller couples with both the regulator and DC-to-DC converter, and the controller is configured to activate and deactivate the regulator and the DC-to-DC converter depending on an output demand. In one embodiment, the controller is configured to…
Zener-like trim device in polysilicon
Granted: September 16, 2003
Patent Number:
6621138
A semiconductor device includes a polysilicon layer in which a first region of a first conductivity type and a second region of a second conductivity type is formed. The first region and the second region form a p-n junction in the polysilicon layer. The semiconductor device further includes a first metallization region in electrical contact with the first region and a second metallization region in electrical contact with the second region. In operation, a low resistance path is formed…
