Universal output driver
Granted: September 2, 2003
Patent Number:
6614666
A circuit for driving a communication line includes a transformer having a secondary winding for supplying an output drive signal, and having a primary winding connected to conduct current through a control element that receives a control signal which stabilizes the amplitude of output drive signal, independent of variations in supply voltage. A control circuit produces the control signal in response to the difference of signals produced across conductive elements that are connected to…
Tandem Si-Ge solar cell with improved conversion efficiency
Granted: September 2, 2003
Patent Number:
6613974
P-type and n-type regions are defined in the first surface of a substrate upon which is formed an epitaxial layer of preferably Si—Ge material, preferably capped by Si material. During epitaxy formation, dopant in the defined regions diffuses down to form p-type and n-type junctions in the Si material, and diffuses up to form p-type and n-type junctions in the Si—Ge epitaxial material. Si junctions are buried beneath the surface and are surface recombination velocity effects…
Differential window comparator
Granted: August 12, 2003
Patent Number:
6605965
A window comparator is disclosed having a 1st and a 2nd voltage input wherein the window comparator is fully differential with respect to the 1st and 2nd voltage inputs. Two differential pairs control the state of a zero-crossing comparator in response to the difference between the 1st and 2nd voltage inputs.
Voltage-controlled variable duty-cycle oscillator
Granted: July 29, 2003
Patent Number:
6600379
A voltage-controlled variable duty-cycle oscillator includes a current generator whose current Iref mirrored in three one-shots that each include two pair of series-coupled MOS transistors and a timing capacitor. The timing capacitor is precharged to Vcc in the first two one-shots, and to a lesser voltage Vcon in the third one-shot. The oscillator also includes pre and a post-NOR-gate logic. Output signals from the two one-shots are coupled to the pre NOR-gate logic to generate an…
LDMOS field effect transistor with improved ruggedness in narrow curved areas
Granted: July 15, 2003
Patent Number:
6593621
A lateral DMOS transistor incorporates one or more enhancement schemes for improving the breakdown voltage characteristics and ruggedness of the transistor. In one embodiment, the drain region of the lateral DMOS transistor is separated from the body region by a first distance in the rectilinear region necessary to achieve a first breakdown voltage, and separated by a second distance in the curved region necessary to achieve at least the first breakdown voltage, the second distance being…
Low voltage, low power operational amplifier with rail to rail output
Granted: July 8, 2003
Patent Number:
6590980
A novel operational amplifier is disclosed which is divided into an input stage, a common mode feedback stage and an output stage. The output of the operational amplifier swings rail to rail, and the input may swing nearly rail to rail. The operational amplifier combines fast response with low power consumption and low supply voltage.
Output stage and method of enhancing output gain
Granted: July 1, 2003
Patent Number:
6586998
The present invention provides for an output stage which couples with an input stage and is configured to limit a reflection current which is reflected back into the input stage to enhanced an output voltage to drive a variety of loads. The present output stage limits the reflection current by compensating for at least one bias current at the input stage output. The output stage further reduced a quiescent current needed to maintain the output stage in an active state without adversely…
Ring topology based voltage controlled oscillator
Granted: July 1, 2003
Patent Number:
6587007
A VCO includes N delay stages that each contribute 180°/N phase shift at the VCO frequency of interest and provide a tunable selection of at least a fast delay and a slow delay path. Each delay stage includes a delay interpolator that smoothly interpolates between the delay paths within the stage. Each delay stage is coupled to a bandpass frequency selective network that acts as a load and helps filter phase noise. Feedback from the Nth delay stage to the first delay stage is via a…
Electrostatic discharge protection for integrated semiconductor devices using channel stop field plates
Granted: June 24, 2003
Patent Number:
6583476
A semiconductor structure which protects against damages to an integrated circuit caused by electrostatic discharge (ESD) at a power supply pin includes a channel stop field plate coupled between a power supply terminal associated with the power supply pin and contacts to N-type substrate or N-wells formed in the semiconductor structure receiving the power supply voltage. The field plate functions to inhibit surface leakage current and is also used to introduce a resistance between the…
Method and system for providing a power lateral PNP transistor using a buried power buss
Granted: May 20, 2003
Patent Number:
6566733
A power lateral PNP device is disclosed which includes an epitaxial layer; a first and second collector region embedded in the epitaxial layer; an emitter region between the first and second collector regions. Therefore slots are placed in each of the regions. Accordingly, in a first approach the standard process flow will be followed until reaching the point where contact openings and metal are to be processed. In this approach slots are etched that are preferably 5 to 6 um deep and 5…
Universally stable output filter
Granted: April 22, 2003
Patent Number:
6552629
In accordance with the teachings of this invention a novel method and apparatus is taught which provides for the stabilizing of an output signal through an output circuit having a compensation circuit coupled with an output capacitor, such that the compensation circuit is configured to compensate for an equivalent series resistance of the output capacitor. The compensation circuit compensates for the equivalent series resistance by providing a shift in a phase of the output signal to…
Voltage-controlled oscillator frequency auto-calibrating system
Granted: April 8, 2003
Patent Number:
6545545
A voltage-controlled oscillator auto-calibrating system is disclosed that performs center-frequency calibration of a VCO. A frequency range detector monitors the VCO frequency and provides coarse adjustments so that the target frequency is within the capture range of the VCO's fine-tuning voltage. A lock detector monitors the phase-locked loop circuit and triggers an adjustment after the phase-locked loop circuit achieves lock. A monotonicity check circuit provides VCO frequency…
Voltage-controlled oscillator frequency range detector
Granted: November 19, 2002
Patent Number:
6483387
A voltage-controlled oscillator frequency range detector is disclosed that detects when the voltage-controlled oscillator frequency within a phase-locked loop is out of range and indicates the required direction of the frequency adjustment. The voltage-controlled oscillator frequency range detector includes a comparator circuit, which receives a voltage-controlled oscillator control voltage signal, and a frequency detector circuit, which receives a reference clock signal and a…
Charge pump leakage current compensation systems and methods
Granted: October 29, 2002
Patent Number:
6473485
A leakage current compensation system and method is disclosed that reduces frequency spurs and phase offset in a frequency synthesizer. The leakage current is determined based on the phase offset of the frequency synthesizer relative to a reference clock. A leakage current compensation circuit provides a leakage current compensation signal to the frequency synthesizer at the loop filter terminals to minimize the phase offset.
Linear two quadrant voltage regulator
Granted: August 20, 2002
Patent Number:
6437638
The present invention provides an apparatus and method for regulating an output to stabilize the output without limiting an output current. The regulator includes a stabilizing circuit coupled to a source circuit and a sink circuit. The source circuit is configured to source the output current to the output, and the sink circuit is configured to sink the output current from the output. The stabilizing circuit is configured to transition the source circuit and the sink circuit between a…
Adding a laplace transform zero to a linear integrated circuit for frequency stability
Granted: July 23, 2002
Patent Number:
6424132
A compensation circuit for introducing a zero in a first circuit being incorporated in a closed loop feedback system includes a first capacitor, an amplifier and a second capacitor, connected in series between an input node and a summing node in the first circuit. In one embodiment, the summing node is coupled to a summing circuit disposed between two gain stages of an error amplifier in the first circuit. In another embodiment, the summing node is coupled to the output node of the error…
Method and system for reliably providing a lock indication
Granted: June 25, 2002
Patent Number:
6411130
In a first aspect, a lock indicator circuit is disclosed. The lock indicator comprises a first circuit for providing a first beat signal; and a second circuit for providing a second beat signal. A reference clock signal and a recovered clock signal are provided in a reversed manner to the first and second circuits. In a second aspect, a method for providing a lock indication of a circuit is disclosed. The method comprises the steps of providing a first and second beat signals; and…
Lock detector for a dual phase locked loop system
Granted: June 25, 2002
Patent Number:
6411143
A dual phase locked loop (PLL) lock detector is disclosed using a single lock detector to determine whether a dual PLL system is in a lock condition. In one embodiment, a VCO clock output from a master PLL is frequency divided to form a reference clock for a slave PLL. The lock detector monitors the slave PLL only when it determines that the master PLL is locked.
Selective substrate implant process for decoupling analog and digital grounds
Granted: May 28, 2002
Patent Number:
6395591
An integrated circuit fabrication process includes a selective substrate implant process to effectively decouple a first power supply connection from a second power supply connection while providing immunity against parasitic effects. In one embodiment, the selective substrate implant process forms heavily doped p-type regions only under P-wells in which noise producing circuitry are built. The noisy ground connection for these P-wells are decoupled from the quiet ground connection for…
Transconductance amplifier circuit
Granted: May 28, 2002
Patent Number:
6396311
A reference-corrected ratiometric current sensing circuit for sensing a current flowing through a load and a power-controlling pass device includes a sense device, a sense resistor, and a variable reference current source for providing a varying reference current. The varying reference current is varied according to a ratio of the voltage across the sense device to the voltage across the pass device. The ratiometric current sensing circuit of the present invention is capable of accurate…
