Atomic layer removal for high aspect ratio gapfill
Granted: July 19, 2011
Patent Number:
7981763
Methods of filling high aspect ratio, narrow width (e.g., sub-50 nm) gaps on a substrate are provided. The methods provide gap fill with little or no incidence of voids, seams or weak spots. According to various embodiments, the methods depositing dielectric material in the gaps to partially fill the gaps, then performing multi-step atomic layer removal process to selectively etch unwanted material deposited on the sidewalls of the gaps. The multi-step atomic layer removal process…
Methods of depositing stable and hermetic ashable hardmask films
Granted: July 19, 2011
Patent Number:
7981777
The present invention provides PECVD methods for forming stable and hermetic ashable hard masks (AHMs). The methods involve depositing AHMs using dilute hydrocarbon precursor gas flows and/or high LFRF/HFRF ratios. In certain embodiments, the AHMs are transparent and have high etch selectivities. Single and dual layer hermetic AHM stacks are also provided. According to various embodiments, the dual layer stack includes an underlying AHM layer having tunable optical properties and a…
Methods of depositing highly selective transparent ashable hardmask films
Granted: July 19, 2011
Patent Number:
7981810
The present invention addresses this need by providing a method for forming transparent PECVD deposited ashable hardmasks (AHMs) that have high plasma etch selectivity to underlying layers. Methods of the invention involve depositing the AHM using dilute hydrocarbon precursor gas flows and/or low process temperatures. The AHMs produced are transparent (having absorption coefficients of less than 0.1 in certain embodiments). The AHMs also have the property of high selectivity of the hard…
Plasma reactor showerhead face plate having concentric ridge pattern
Granted: July 19, 2011
Patent Number:
D641829
Methods for removing silicon nitride and other materials during fabrication of contacts
Granted: July 12, 2011
Patent Number:
7977249
Methods for removing silicon nitride and elemental silicon during contact preclean process involve converting these materials to materials that are more readily etched by fluoride-based etching methods, and subsequently removing the converted materials by a fluoride-based etch. Specifically, silicon nitride and elemental silicon may be treated with an oxidizing agent, e.g., with an oxygen-containing gas in a plasma, or with O2 or O3 in the absence of plasma to produce a material that is…
Fabrication of semiconductor interconnect structure
Granted: July 5, 2011
Patent Number:
7972970
An etching process for selectively etching exposed metal surfaces of a substrate and forming a conductive capping layer over the metal surfaces is described. In some embodiments, the etching process involves oxidation of the exposed metal to form a metal oxide that is subsequently removed from the surface of the substrate. The exposed metal may be oxidized by using solutions containing oxidizing agents such as peroxides or by using oxidizing gases such as those containing oxygen or…
VLSI fabrication processes for introducing pores into dielectric materials
Granted: July 5, 2011
Patent Number:
7972976
Porous dielectric layers are produced by introducing pores in pre-formed composite dielectric layers. The pores may be produced after the barrier material, the metal or other conductive material is deposited to form a metallization layer. In this manner, the conductive material is provided with a relatively smooth continuous surface on which to deposit.
Method of electroplating using a high resistance ionic current source
Granted: June 28, 2011
Patent Number:
7967969
A substantially uniform layer of a metal is electroplated onto a work piece having a seed layer thereon. This is accomplished by employing a “high resistance ionic current source,” which solves the terminal problem by placing a highly resistive membrane (e.g., a microporous ceramic or fretted glass element) in close proximity to the wafer, thereby swamping the system's resistance. The membrane thereby approximates a constant current source. By keeping the wafer close to the membrane…
Low-K SiC copper diffusion barrier films
Granted: June 28, 2011
Patent Number:
7968436
Copper diffusion barrier films having low dielectric constants are suitable for a variety of copper/inter-metal dielectric integration schemes. Copper diffusion barrier films in accordance with the invention are composed of one or more layers of silicon carbide, at least one of the silicon carbide layers having a composition of at least 40% carbon (C), for example, between about 45 and 60% carbon (C). The films' high carbon-content layer will have a composition wherein the ratio of C to…
Two step copper electroplating process with anneal for uniform across wafer deposition and void free filling on ruthenium coated wafers
Granted: June 21, 2011
Patent Number:
7964506
A two-step semiconductor electroplating process deposits copper onto wafers coated with a semi-noble metal in manner that is uniform across the wafer and free of voids after a post electrofill anneal. A seed-layer plating bath nucleates copper uniformly and conformably at a high density in a very thin film using a unique pulsed waveform. The wafer is then annealed before a second bath fills the features. The seed-layer anneal improves adhesion and stability of the semi-noble to copper…
PVD-based metallization methods for fabrication of interconnections in semiconductor devices
Granted: June 21, 2011
Patent Number:
7964504
Recessed features on a Damascene substrate are filled with metal using plasma PVD. Recessed features having widths of less than about 300 nm, e.g., between about 30-300 nm can be filled with metals (e.g., copper and aluminum), without forming voids. In one approach, the deposition is performed by exposing the substrate to a high-density plasma characterized by high fractional ionization of metal. Under these conditions, the metal is deposited within the recess, without forming large…
Load lock design for rapid wafer heating
Granted: June 14, 2011
Patent Number:
7960297
A semiconductor processing tool heats wafers using radiant heat and resistive heat in chamber or in a load lock where pressure changes. The wafers are heated in greater part with a resistive heat source until a transition temperature or pressure is reached, then they are heated in greater part with a radiant heat source. Throughput improves for the tool because of the wafers can reach a high temperature uniformly in seconds.
Methods for growing low-resistivity tungsten for high aspect ratio and small features
Granted: June 7, 2011
Patent Number:
7955972
The present invention addresses this need by providing methods for depositing low resistivity tungsten films in small features and features having high aspect ratios. The methods involve depositing very thin tungsten nucleation layers by pulsed nucleation layer (PNL) processes and then using chemical vapor deposition (CVD) to deposit a tungsten layer to fill the feature. Depositing the tungsten nucleation layer involves exposing the substrate to alternating pulses of a boron-containing…
Method for improved thickness repeatability of PECVD deposited carbon films
Granted: June 7, 2011
Patent Number:
7955990
Provided herein are improved methods of depositing carbon-based films using acetylene as a precursor. The methods involve using a low-vapor pressure solvent, e.g., dimethylfluoride (DMF) to stabilize the acetylene and delivering the acetylene to a deposition chamber. The methods provide improved wafer-to-wafer thickness uniformity and increase the usable amount of acetylene in an acetylene source to over 95%.
In-situ process layer using silicon-rich-oxide for etch selectivity in high AR gapfill
Granted: May 31, 2011
Patent Number:
7951683
In-situ semiconductor process that can fill high aspect ratio (typically at least 6:1, for example 7:1 or higher), narrow width (typically sub 0.13 micron, for example 0.1 micron or less) gaps with significantly reduced incidence of voids or weak spots is provided. This deposition part of the process may involve the use of any suitable high density plasma chemical vapor deposition (HDP CVD) chemistry. Prior to etch back, the feature gap is plugged with an etch selectivity layer. The etch…
Photoresist-free metal deposition
Granted: May 24, 2011
Patent Number:
7947163
Selectively accelerated or selectively inhibited metal deposition is performed to form metal structures of an electronic device. A desired pattern of an accelerator or of an inhibitor is applied to the substrate; for example, by stamping the substrate with a patterned stamp or spraying a solution using an inkjet printer. In other embodiments, a global layer of accelerator or inhibitor is applied to a substrate and selectively modified in a desired pattern. Thereafter, selective metal…
Pedestal heat transfer and temperature control
Granted: May 10, 2011
Patent Number:
7941039
Provided herein are assemblies that, when coupled to an object, are capable of keeping the object at a uniform elevated temperature while removing large amounts of heat from an external source. Applications include various integrated circuit fabrication processes that use such external sources to expose wafers to radiation. In certain embodiments, the assemblies include a pedestal for supporting the wafer or other object. In certain embodiments, the assemblies include a calibrated heat…
Rapidly cleanable electroplating cup assembly
Granted: May 3, 2011
Patent Number:
7935231
Embodiments of a closed-contact electroplating cup assembly that may be rapidly cleaned while an electroplating system is on-line are disclosed. One disclosed embodiment comprises a cup assembly and a cone assembly, wherein the cup assembly comprises a cup bottom comprising an opening, a seal surrounding the opening, an electrical contact structure comprising a plurality of electrical contacts disposed around the opening, and an interior cup side that is tapered inwardly in along an…
Measuring in-situ UV intensity in UV cure tool
Granted: May 3, 2011
Patent Number:
7935940
Consistent ultraviolet (UV) intensity for a semiconductor UV cure chamber is measured in-situ with a hot pedestal in vacuum by measuring reflected UV light from a calibration substrate at a UV detector mounted in the lamp assembly. The measurement apparatus includes a UV detector, a cover that protects the detector from UV light while not in use, and a mirror disposed between the chamber window and the UV detector. Measured UV intensity from the substrate reflection and from the mirror…
Method and apparatus for increasing local plasma density in magnetically confined plasma
Granted: April 12, 2011
Patent Number:
7922880
Local plasma density, e.g., the plasma density in the vicinity of the substrate, is increased by providing an ion extractor configured to transfer ions and electrons from a first region of magnetically confined plasma (typically a region of higher density plasma) to a second region of plasma (typically a region of lower density plasma). The second region of plasma is preferably also magnetically shaped or confined and resides between the first region of plasma and the substrate. A…
