Method to improve mechanical strength of low-K dielectric film using modulated UV exposure
Granted: October 25, 2011
Patent Number:
8043667
Methods and apparatus for improving mechanical properties of a dielectric film on a substrate are provided. In some embodiments, the dielectric film is a carbon-doped oxide (CDO). The methods involve the use of modulated ultraviolet radiation to increase the mechanical strength while limiting shrinkage and limiting any increases in the dielectric constant of the film. Methods improve film hardness, modulus and cohesive strength, which provide better integration capability and improved…
Capping before barrier-removal IC fabrication method
Granted: October 25, 2011
Patent Number:
8043958
Methods of forming a capping layer on conductive lines in a semiconductor device may be characterized by the following operations: (a) providing a semiconductor substrate comprising a dielectric layer having (i) exposed conductive lines (e.g., copper lines) disposed therein, and (ii) an exposed barrier layer disposed thereon; and (b) depositing a capping layer material on at least the exposed conductive lines of the semiconductor substrate. In certain embodiments, the method may also…
Process for through silicon via filling
Granted: October 25, 2011
Patent Number:
8043967
A semiconductor electroplating process deposits copper into the through silicon via hole to completely fill the through silicon via in a substantially void free is disclosed. The through silicon via may be more than about 3 micrometers in diameter and more that about 20 micrometers deep. High copper concentration and low acidity electroplating solution is used for deposition copper into the through silicon vias.
Adsorption based material removal process
Granted: October 25, 2011
Patent Number:
8043972
Methods for accurate and conformal removal of atomic layers of materials make use of the self-limiting nature of adsorption of at least one reactant on the substrate surface. In certain embodiments, a first reactant is introduced to the substrate in step (a) and is adsorbed on the substrate surface until the surface is partially or fully saturated. A second reactant is then added in step (b), reacting with the adsorbed layer of the first reactant to form an etchant. The amount of an…
Methods and apparatus for resputtering process that improves barrier coverage
Granted: October 25, 2011
Patent Number:
8043484
Conductive or barrier material is deposited on a semiconductor substrate having recessed features by a method that has at least two operations. The first operation involves depositing a layer of the material on at least a portion of the field regions of the wafer. The second operation involves resputtering at least the layer residing on the field region of the wafer under high pressure. If the pressure is sufficiently high, momentum transfer reflection of the resputtered material will…
Nanoparticle cap layer
Granted: October 18, 2011
Patent Number:
8039379
Functionalized nanoparticles are deposited on metal lines inlaid in dielectric to form a metal cap layer that reduces electromigration in the metal line. The functionalized nanoparticles are deposited onto activated metal surfaces, then sintered and annealed to remove the functional agents leaving behind a continuous capping layer. The resulting cap layer is about 1 to 10 nm thick with 30-100% atomic of the nanoparticle material. Various semiconductor processing tools may be adapted for…
Loadlock designs and methods for using same
Granted: October 11, 2011
Patent Number:
8033769
Provided are apparatuses and methods disclosed for wafer processing. Specific embodiments include dual wafer handling systems that transfer wafers from storage cassettes to processing modules and back and aspects thereof. Stacked independent loadlocks that allow venting and pumping operations to work in parallel and may be optimized for particle reduction are provided. Also provided are annular designs for radial top down flow during loadlock vent and pumpdown.
Minimum contact area wafer clamping with gas flow for rapid wafer cooling
Granted: October 11, 2011
Patent Number:
8033771
Apparatuses and methods for cooling and transferring wafers from low pressure environment to high pressure environment are provided. An apparatus may include a cooling pedestal and a set of supports for holding the wafer above the cooling pedestal. The average gap between the wafer and the cooling pedestal may be no greater than about 0.010 inches. Venting gases may be used to increase the pressure inside the apparatus during the transfer. In certain embodiment, venting gases comprise…
Treatment of low K films with a silylating agent for damage repair
Granted: October 11, 2011
Patent Number:
8034638
The present invention provides methods of repairing damage to low-k dielectric film that is incurred by commonly used processes in IC fabrication. The methods may be integrated into an IC fabrication process flow at various stages. According to various embodiments, the methods of involve performing an IC fabrication process on a wafer on which a low-k film is deposited, and subsequently treating the film with a silylating agent to repair the damage done to the film during the process.…
Method of eliminating small bin defects in high throughput TEOS films
Granted: October 11, 2011
Patent Number:
8034725
This invention provides a high throughput PECVD process for depositing TEOS films in a multi-station sequential deposition chamber. The methods significantly reduce the number of particles in the TEOS films, thereby eliminating or minimizing small bin defects. The methods of the invention involve dedicating a first station for temperature soak while flowing purge gas. Stopping the flow of reactant gas and flowing the purge gas for station 1 eliminates TEOS condensation on a cold wafer…
Protection of Cu damascene interconnects by formation of a self-aligned buffer layer
Granted: October 4, 2011
Patent Number:
8030777
Methods of protecting exposed metal damascene interconnect surfaces in a process for making electronic components and the electronic components made according to such methods. An integrated circuit structure having damascene regions with exposed metal surfaces is provided into a closed processing chamber, whereby a first reactant is contacted to the exposed metal surfaces to transform a top portion of the metal layer into a protective self-aligned buffer layer. Reacting molecules of the…
Sequential station tool for wet processing of semiconductor wafers
Granted: September 27, 2011
Patent Number:
8026174
Methods and apparatus are provided for processing semiconductor wafers sequentially. Sequential processes employ multi-station processing modules, where particular encompassing wafer processes are divided into sub-processes, each optimized for increasing wafer to wafer uniformity, result quality, and overall wafer throughput. In one example, a copper electroplating module includes separate stations for wetting, initiation, seed layer repair, fill, overburden, reclaim, and rinse.
Protective self-aligned buffer layers for damascene interconnects
Granted: September 20, 2011
Patent Number:
8021486
Capping protective self aligned buffer (PSAB) layers are layers of material that are selectively formed at the surface of metal layers in a partially fabricated semiconductor device. Encapsulating PSAB layers are formed not only at the surface of the metal layers, but also within the unexposed portions of the metal lines. Encapsulating PSAB layer, for example, can surround the metal line with the PSAB material, thereby protecting interfaces between the metal line and diffusion barriers.…
Deposition of doped copper seed layers having improved reliability
Granted: September 13, 2011
Patent Number:
8017523
Improved methods of depositing copper seed layers in copper interconnect structure fabrication processes are provided. Also provided are the resulting structures, which have improved electromigration performance and reduced line resistance. According to various embodiments, the methods involve depositing a copper seed bilayer on a barrier layer in a recessed feature on a partially fabricated semiconductor substrate. The bilayer has a copper alloy seed layer and a pure copper seed layer,…
Method and apparatus to reduce defects in liquid based PECVD films
Granted: September 13, 2011
Patent Number:
8017527
Apparatuses and methods for diverting a flow of a liquid precursor during flow stabilization and plasma stabilization stages during PECVD processes are effective at eliminating particle defects in PECVD films deposited using a liquid precursor.
Methods of forming moisture barrier for low K film integration with anti-reflective layers
Granted: August 23, 2011
Patent Number:
8003549
A nitrogen-free anti-reflective layer for use in semiconductor photolithography is fabricated in a chemical vapor deposition process, optionally plasma-enhanced, using a gaseous mixture of carbon, silicon, and oxygen sources. By varying the process parameters, a substantially hermetic layer with acceptable values of the refractive index n and extinction coefficient k can be obtained. The nitrogen-free moisture barrier anti-reflective layer produced by this technique improves plasma etch…
Method for making high stress boron-doped carbon films
Granted: August 16, 2011
Patent Number:
7998881
Transistor architectures and fabrication processes generate channel strain without adversely impacting the efficiency of the transistor fabrication process while preserving the material quality and enhancing the performance of the resulting transistor. Transistor strain is generated is PMOS devices using a highly compressive post-salicide boron doped carbon capping layer applied as a blanket over on at least the source and drain regions. The stress from this capping layer is uniaxially…
Deposition sub-chamber with variable flow
Granted: August 9, 2011
Patent Number:
7993457
An apparatus and method for depositing film on a substrate includes a plurality of conduits that allow by-product and reactant gases to flow past the edge of a substrate. The apparatus and process of the present invention has several advantages for enhanced chamber performance, particularly for micro-volume chambers using pulsed deposition layer processes.
Nanoparticle cap layer
Granted: August 9, 2011
Patent Number:
7994640
Functionalized nanoparticles are deposited on metal lines inlaid in dielectric to form a metal cap layer that reduces electromigration in the metal line. The functionalized nanoparticles are deposited onto activated metal surfaces, then sintered and annealed to remove the functional agents leaving behind a continuous capping layer. The resulting cap layer is about 1 to 10 nm thick with 30-100% atomic of the nanoparticle material. Various semiconductor processing tools may be adapted for…
Closed contact electroplating cup assembly
Granted: July 26, 2011
Patent Number:
7985325
Embodiments of a closed-contact electroplating cup are disclosed. One embodiment comprises a cup bottom comprising an opening, and a seal disposed on the cup bottom around the opening. The seal comprises a wafer-contacting peak located substantially at an inner edge of the seal. The embodiment also comprises an electrical contact structure disposed over a portion of the seal, wherein the electrical contact structure comprises an outer ring and a plurality of contacts extending inwardly…
