Methods and apparatus for engineering an interface between a diffusion barrier layer and a seed layer
Granted: December 21, 2010
Patent Number:
7855147
Copper seed layers are formed on diffusion barrier layers (e.g., on Ta, and TaNx layers) without significant agglomeration of copper, with the use of an engineered barrier layer/seed layer interface. The engineered interface includes an adhesion layer, in which copper atoms are physically trapped and are prevented from migrating and agglomerating. The adhesion layer can include between about 20-80% atomic of copper. The copper atoms of the adhesion layer are exposed during deposition of…
Method and apparatus for electroplating including remotely positioned second cathode
Granted: December 21, 2010
Patent Number:
7854828
An apparatus for electroplating a layer of metal on the surface of a wafer includes a second cathode located remotely with respect to the wafer. The remotely positioned second cathode allows modulation of current density at the wafer surface during an entire electroplating process. The second cathode diverts a portion of current flow from the near-edge region of the wafer and improves the uniformity of plated layers. The remote position of second cathode allows the insulating shields…
UV treatment for carbon-containing low-k dielectric repair in semiconductor processing
Granted: December 14, 2010
Patent Number:
7851232
A method for the ultraviolet (UV) treatment of carbon-containing low-k dielectric enables process-induced damage repair. The method is particularly applicable in the context of damascene processing. A method provides for forming a semiconductor device by depositing a carbon-containing low-k dielectric layer on a substrate and forming a trench in the low-k dielectric layer, the trench having sidewalls ending at a bottom. The trench is then exposed to UV radiation and, optionally a gas…
Low-k b-doped SiC copper diffusion barrier films
Granted: November 30, 2010
Patent Number:
7842604
The present invention provides a low dielectric constant copper diffusion barrier film composed, at least in part, of boron-doped silicon carbide suitable for use in a semiconductor device and methods for fabricating such a film. The copper diffusion barrier maintains a stable dielectric constant of less than 4.5 in the presence of atmospheric moisture.
Atomic layer profiling of diffusion barrier and metal seed layers
Granted: November 30, 2010
Patent Number:
7842605
Material is removed from a substrate surface (e.g., from a bottom portion of a recessed feature on a partially fabricated semiconductor substrate) by subjecting the surface to a plurality of profiling cycles, wherein each profiling cycle includes a net etching operation and a net depositing operation. An etching operation removes a greater amount of material than is being deposited by a depositing operation, thereby resulting in a net material etch-back per profiling cycle. About 2-10…
Method for purifying acetylene gas for use in semiconductor processes
Granted: October 26, 2010
Patent Number:
7820556
Acetylene is treated to remove some residual storage solvent that may be present with the acetylene in a source of acetylene such as a container. Such treatment may be performed prior to supplying the acetylene to a deposition chamber or other reactor where acetylene is a reactant. After treatment, the acetylene gas stream has a relatively constant concentration of storage solvent, regardless of how much acetylene has been released from the acetylene source. The treatment may involve…
High throughput servo load cup with integrated wet chemistry delivery
Granted: October 12, 2010
Patent Number:
7811153
A work piece handling apparatus moves workpieces with a plurality of independently movable load cups that have combined multiple axes of motion. The apparatus can load and unload work pieces from a wet process station and move work pieces between wet process stations and maintain wet chemistry delivery to the workpiece without involving a robot. A method of work piece handling using the apparatus provides a significant throughput improvement by reducing the inherent time lag of pneumatic…
Capping before barrier-removal IC fabrication method
Granted: October 12, 2010
Patent Number:
7811925
Methods of forming a capping layer on conductive lines in a semiconductor device may be characterized by the following operations: (a) providing a semiconductor substrate comprising a dielectric layer having (i) exposed conductive lines (e.g., copper lines) disposed therein, and (ii) an exposed barrier layer disposed thereon; and (b) depositing a capping layer material on at least the exposed conductive lines of the semiconductor substrate. In certain embodiments, the method may also…
Substrate temperature control in an ALD reactor
Granted: October 5, 2010
Patent Number:
7806983
A deposition system includes a process chamber for conducting an ALD process to deposit layers on a substrate. An electrostatic chuck (ESC) retains the substrate. A backside gas increases thermal coupling between the substrate and the ESC. The ESC is cooled via a coolant flowing through a coolant plate and heated via a resistive heater. Various arrangements are disclosed.
Interfacial layers for electromigration resistance improvement in damascene interconnects
Granted: September 21, 2010
Patent Number:
7799671
Protective caps residing at an interface between metal lines and dielectric diffusion barrier (or etch stop) layers are used to improve electromigration performance of interconnects. Protective caps are formed by depositing a source layer of dopant-generating material (e.g., material generating B, Al, Ti, etc.) over an exposed copper line, converting the upper portion of the source layer to a passivated layer (e.g., nitride or oxide) while allowing an unmodified portion of a…
Methods for producing low stress porous low-k dielectric materials using precursors with organic functional groups
Granted: September 21, 2010
Patent Number:
7799705
Methods of preparing a low stress porous low-k dielectric material on a substrate are provided. The methods involve the use of a structure former precursor and/or porogen precursor with one or more organic functional groups. In some cases, the structure former precursor has carbon-carbon double or triple bonds. In other cases, one or both of the structure former precursor and porogen precursor has one or more bulky organic groups. In other cases, the structure former precursor has…
Two step process for uniform across wafer deposition and void free filling on ruthenium coated wafers
Granted: September 21, 2010
Patent Number:
7799684
A two-step semiconductor electroplating process deposits copper onto wafers coated with a semi-noble metal in manner that is uniform across the wafer and free of voids. A plating bath nucleates copper uniformly and conformably at a high density in a very thin film. A second bath fills the features. A unique pulsed waveform enhances the nucleation density and reduces resistivity of the very thin film deposited in the nucleation operation. The process produces a thinner and conformal…
Selective electrochemical accelerator removal
Granted: September 21, 2010
Patent Number:
7799200
Methods and apparatus are provided for planar metal plating on a workpiece having a surface with recessed regions and exposed surface regions; comprising the steps of: causing a plating accelerator to become attached to said surface including the recessed and exposed surface regions; selectively removing the plating accelerator from the exposed surface regions without performing substantial metal plating on the surface; and after removal of plating accelerator is at least partially…
Sequential deposition/anneal film densification method
Granted: September 7, 2010
Patent Number:
7790633
A silicon dioxide-based dielectric layer is formed on a substrate surface by a sequential deposition/anneal technique. The deposited layer thickness is insufficient to prevent substantially complete penetration of annealing process agents into the layer and migration of water out of the layer. The dielectric layer is then annealed, ideally at a moderate temperature, to remove water and thereby fully densify the film. The deposition and anneal processes are then repeated until a desired…
Edge bevel removal of copper from silicon wafers
Granted: August 24, 2010
Patent Number:
7780867
Chemical etching methods and associated modules for performing the removal of metal from the edge bevel region of a semiconductor wafer are described. The methods and systems apply liquid etchant in a precise manner at the edge bevel region of the wafer, so that the etchant is applied on to the front edge, the side edge and the back edge. The etchant thus does not flow or splatter onto the active circuit region of the wafer. An edge bevel removal embodiment involving that is particularly…
Resputtering process for eliminating dielectric damage
Granted: August 24, 2010
Patent Number:
7781327
Methods of resputtering material from the wafer surface include at least one operation of resputtering material under a pressure of at least 10 mTorr. The methods can be used in conjunction with an iPVD apparatus, such as hollow cathode magnetron (HCM) or planar magnetron. The resputtered material may be a diffusion barrier material or a conductive layer material. The methods provide process conditions which minimize the damage to the dielectric layer during resputtering. The methods…
Methods for producing low-k carbon doped oxide films with low residual stress
Granted: August 24, 2010
Patent Number:
7781351
Methods of preparing a carbon doped oxide (CDO) layer of low dielectric constant and low residual stress involving, for instance, providing a substrate to a deposition chamber and exposing it to an organosilicon precursor containing unsaturated C—C bonds or to multiple organic precursors including at least one organosilicon and at least one unsaturated C—C bond are provided. The methods may also involve igniting and maintaining a plasma in a deposition chamber using radio frequency…
Process for through silicon via filing
Granted: August 17, 2010
Patent Number:
7776741
A semiconductor electroplating process deposits copper into the through silicon via hole to completely fill the through silicon via in a substantially void free is disclosed. The through silicon via may be more than about 3 micrometers in diameter and more that about 20 micrometers deep. High copper concentration and low acidity electroplating solution is used for deposition copper into the through silicon vias.
Method for improving uniformity and adhesion of low resistivity tungsten film
Granted: August 10, 2010
Patent Number:
7772114
Methods of improving the uniformity and adhesion of low resistivity tungsten films are provided. Low resistivity tungsten films are formed by exposing the tungsten nucleation layer to a reducing agent in a series of pulses before depositing the tungsten bulk layer. According to various embodiments, the methods involve reducing agent pulses with different flow rates, different pulse times and different interval times.
Gas-purged vacuum valve
Granted: July 13, 2010
Patent Number:
7754014
A vacuum valve assembly for use in a vacuum processing chamber includes a seat defining an opening in the vacuum valve, with the seat having a sealing face adjacent the opening and normal to the direction of the opening; and a gate having a sealing face adapted to mate with the seat sealing face, the gate being movable toward and away from the seat sealing face to seal and open the vacuum valve opening. A continuous elastomeric seal extends around the vacuum valve opening between the…
