Reducing silicon attack and improving resistivity of tungsten nitride film
Granted: July 13, 2010
Patent Number:
7754604
The present invention provides improved methods of depositing tungsten-containing films on substrates, particularly on silicon substrates. The methods involve depositing an interfacial or “flash” layer of tungsten on the silicon prior to deposition of tungsten nitride. The tungsten flash layer is typically deposited by a CVD reaction of a tungsten precursor and a reducing agent. According to various embodiments, the tungsten flash layer may be deposited with a high reducing agent to…
Method for controlling conductor deposition on predetermined portions of a wafer
Granted: July 13, 2010
Patent Number:
7754061
A plating apparatus and method for deposition of a conductive material on a semiconductor wafer having surface portions and cavity portions. A differential in an adsorbed concentration of an additive, including accelerators or suppressors, between a surface portion and a cavity portion of a wafer surface is established in a chamber. A mask or sweeper may be used to establish the differential. After establishing the differential in the chamber, the conductive material is electrodeposited…
PVD-based metallization methods for fabrication of interconnections in semiconductor devices
Granted: June 29, 2010
Patent Number:
7745332
Recessed features on a Damascene substrate are filled with metal using plasma PVD. Recessed features having widths of less than about 300 nm, e.g., between about 30-300 nm can be filled with metals (e.g., copper and aluminum), without forming voids. In one approach, the deposition is performed by exposing the substrate to a high-density plasma characterized by high fractional ionization of metal. Under these conditions, the metal is deposited within the recess, without forming large…
Method for improving process control and film conformality of PECVD film
Granted: June 29, 2010
Patent Number:
7745346
A method for forming a silicon-based dielectric film on a substrate with a single deposition process operation using pulsed plasma enhanced chemical vapor deposition (PECVD) wherein the high frequency radio frequency power of the plasma is pulsed, allows enhanced control, efficiency and product quality of the PECVD process. Pulsing the high frequency RF power of the plasma reduces the deposited film thickness per unit time the high frequency RF power of the plasma is on. This yields…
Simultaneous front side ash and backside clean
Granted: June 22, 2010
Patent Number:
7740768
A method and apparatus for cleaning a wafer. The wafer is heated and moved to a processing station within the apparatus that has a platen either permanently in a platen down position or is transferable from a platen up position to the platen down position. The wafer is positioned over the platen so as not to contact the platen and provide a gap between the platen and wafer. The gap may be generated by positioning the platen in a platen down position. A plasma flows into the gap to enable…
Dual seal deposition process chamber and process
Granted: June 15, 2010
Patent Number:
7737035
An apparatus and method for sealing and unsealing a chemical deposition apparatus in a chemical deposition process chamber includes a microvolume that has dual sealing elements at its periphery. One seal, the outer seal, is used to seal the inside of the microvolume from the main process chamber. The second (inner) seal is used to seal the inside of the microvolume from a vacuum source. The apparatus and process of the present invention has several advantages for enhanced chamber…
Method for producing low-K CDO films
Granted: June 15, 2010
Patent Number:
7737525
Methods of preparing a carbon doped oxide (CDO) layers having a low dielectric constant are provided. The methods involve, for instance, providing a substrate to a deposition chamber and exposing it to one or multiple carbon-doped oxide precursors having molecules with at least one carbon-carbon triple bond, or carbon-carbon double bond, or a combination of these groups and depositing the carbon doped oxide dielectric layer under conditions in which the resulting dielectric layer has a…
Plating method and apparatus for controlling deposition on predetermined portions of a workpiece
Granted: June 8, 2010
Patent Number:
7731833
The present invention relates to methods and apparatus for plating a conductive material on a workpiece surface in a highly desirable manner. Using a workpiece-surface-influencing device, such as a mask or sweeper, that preferentially contacts the top surface of the workpiece, relative movement between the workpiece and the workpiece-surface-influencing device is established so that an additive in the electrolyte solution disposed on the workpiece and which is adsorbed onto the top…
Method for depositing a diffusion barrier for copper interconnect applications
Granted: June 8, 2010
Patent Number:
7732314
Methods for forming a metal diffusion barrier on an integrated circuit include at least four operations. The first operation deposits barrier material via PVD, ALD or CVD to provide some minimal coverage. The second operation deposits an additional barrier material and simultaneously etches a portion of the barrier material deposited in the first operation. The third operation deposits barrier material via PVD, ALD or CVD to provide some minimal coverage especially over the bottoms of…
Protective self-aligned buffer layers for damascene interconnects
Granted: June 1, 2010
Patent Number:
7727880
Protective self aligned buffer (PSAB) layers are layers of material that are selectively formed at the surface of metal layers in a partially fabricated semiconductor device. In a Damascene interconnect, PSAB layer typically resides at an interface between the metal layer and a dielectric diffusion barrier layer. PSAB layers promote improved adhesion between a metal layer and an adjacent dielectric diffusion barrier layer. Further, PSAB layers can protect metal surfaces from inadvertent…
H2-based plasma treatment to eliminate within-batch and batch-to-batch etch drift
Granted: June 1, 2010
Patent Number:
7727906
This invention relates to electronic device fabrication for making devices such as semiconductor wafers and resolves the detrimental fluorine loading effect on deposition in the reaction chamber of a HDP CVD apparatus used for forming dielectric layers in high aspect ratio, narrow width recessed features with a repeating dep/etch/dep process. The detrimental fluorine loading effect in the chamber on deposition uniformity is reduced and wafers are provided having less deposition thickness…
Compositionally graded titanium nitride film for diffusion barrier applications
Granted: June 1, 2010
Patent Number:
7727882
A diffusion barrier film includes a layer of compositionally graded titanium nitride, having a nitrogen-rich portion and a nitrogen-poor portion. The nitrogen-rich portion has a composition of at least about 40% (atomic) N, and resides closer to the dielectric than the nitrogen-poor portion. The nitrogen-poor portion has a composition of less than about 30% (atomic) N (e.g., between about 5-30% N) and resides in contact with the metal, e.g., copper. The diffusion barrier film can also…
Protective self-aligned buffer layers for damascene interconnects
Granted: June 1, 2010
Patent Number:
7727881
Protective self aligned buffer (PSAB) layers are layers of material that are selectively formed at the surface of metal layers in a partially fabricated semiconductor device. In a Damascene interconnect, PSAB layer typically resides at an interface between the metal layer and a dielectric diffusion barrier layer. PSAB layers promote improved adhesion between a metal layer and an adjacent dielectric diffusion barrier layer. Further, PSAB layers can protect metal surfaces from inadvertent…
Sonic irradiation during wafer immersion
Granted: June 1, 2010
Patent Number:
7727863
Sonic radiation is applied to a wafer portion of the planar surface of a rotating, tilted wafer as it is being immersed into a liquid treatment bath. The portion includes the leading outer edge region of the wafer. The area of the wafer portion is significantly less than the total surface area of the planar wafer surface. Power density is minimized. As a result, bubbles are removed from the wafer surface and cavitation in the liquid bath is avoided. In some embodiments, the liquid bath…
Apparatus and methods for providing a homogenous I/O interface for controlling a heterogenous mixture of hardware I/O systems
Granted: May 25, 2010
Patent Number:
7725205
Disclosed are apparatus and methods for controlling a heterogeneous mixture of hardware devices in a variety of semiconductor process equipment. In general, a generic Input and Output (I/O) interface is provided between a process management module for specifying control operations and the actual hardware devices of a particular process tool. The process management module generally includes high level processes and/or user interfaces for controlling one or more process tool(s) by…
Protective self-aligned buffer layers for damascene interconnects
Granted: April 27, 2010
Patent Number:
7704873
Capping protective self aligned buffer (PSAB) layers are layers of material that are selectively formed at the surface of metal layers in a partially fabricated semiconductor device. Encapsulating PSAB layers are formed not only at the surface of the metal layers, but also within the unexposed portions of the metal lines. Encapsulating PSAB layer, for example, can surround the metal line with the PSAB material, thereby protecting interfaces between the metal line and diffusion barriers.…
Method of forming contact layers on substrates
Granted: April 27, 2010
Patent Number:
7704880
A method is provided for manufacturing removable contact structures on the surface of a substrate to conduct electricity from a contact member to the surface during electroprocessing. The method comprises forming a conductive layer on the surface. A predetermined region of the conductive layer is selectively coated by a contact layer so that the contact member touches the contact layer as the electroprocessing is performed on the conductive layer.
Method of eliminating small bin defects in high throughput TEOS films
Granted: April 27, 2010
Patent Number:
7704894
This invention provides a high throughput PECVD process for depositing TEOS films in a multi-station sequential deposition chamber. The methods significantly reduce the number of particles in the TEOS films, thereby eliminating or minimizing small bin defects. The methods of the invention involve dedicating a first station for temperature soak while flowing purge gas. Stopping the flow of reactant gas and flowing the purge gas for station 1 eliminates TEOS condensation on a cold wafer…
Method and apparatus for modulation of precursor exposure during a pulsed deposition process
Granted: April 20, 2010
Patent Number:
7700155
A method of depositing material on a substrate comprises providing a reactor with a reaction chamber having a first volume, and contacting a surface of a substrate in the reaction chamber with a first precursor at the first chamber volume to react with and deposit a first layer on the substrate. The method further includes enlarging the reaction chamber to a second, larger volume and removing undeposited first precursor and any excess reaction product to end reaction of the first…
Conductive planarization assembly for electrochemical mechanical planarization of a work piece
Granted: April 13, 2010
Patent Number:
7695597
A conductive planarization assembly for use in electrochemical mechanical planarization is provided. A conductive planarization assembly in accordance with an exemplary embodiment of the invention comprises a first insulating member and a second insulating member overlying the first insulating member and having a plurality of first holes. A conductive member is interposed between the first insulating member and the second insulating member and is electrically coupled to an external…
