Method for preventing metalorganic precursor penetration into porous dielectrics
Granted: April 3, 2007
Patent Number:
7199048
Methods and structures are provided for conformal lining of dual damascene structures in semiconductor devices that contain porous or low k dielectrics. Features, such as trenches and contact vias are formed in the dielectrics. The features are subjected to low-power plasma predeposition treatment to irregularities on the porous surfaces and/or reactively form an permeation barrier before a diffusion barrier material is deposited on the feature. The diffusion barrier may, for example, be…
Method and apparatus for post-CMP cleaning of a semiconductor work piece
Granted: March 27, 2007
Patent Number:
7195548
A method and apparatus are provided for post-CMP cleaning of a semiconductor work piece. The method comprises the steps of subjecting the work piece to a first cleaning composition having one of an acidic pH and a basic pH and subjecting the work piece to a second cleaning composition having an acidic pH, if the first cleaning composition has a basic pH and subjecting the work piece to a second cleaning composition having a basic pH, if the first cleaning composition has an acidic pH.
Electrode assembly for electrochemical processing of workpiece
Granted: March 27, 2007
Patent Number:
7195696
The present invention provides a novel system, apparatus, and method to deposit conductive films on a workpiece. A system for electroplating a surface of a workpiece using a process solution is disclosed. The system comprises a solution housing configured to house an electrode and to contain the process solution, a filter element disposed in the solution housing configured to partition the solution housing into a lower chamber and an upper chamber, and an upper inlet port coupled to the…
Method of electroplating copper layers with flat topography
Granted: March 27, 2007
Patent Number:
7195700
A method of electrochemically filling features on a wafer surface to form a substantially planar copper layer is provided. The features to be filled includes a first feature that is an unfilled feature with the smallest width and a second feature having the next larger width after the smallest feature. The first and the second features are less than 10 micrometers in width. The method comprises applying a first cathodic current to form a first copper layer on the wafer surface. The first…
Methods using eddy current for calibrating a CMP tool
Granted: March 13, 2007
Patent Number:
7189140
Methods and apparatus are provided for calibrating a chemical mechanical polishing (“CMP”) tool having a polishing station with a platen, an eddy current probe disposed within the platen, a polishing pad coupled to the platen, and a metal element disposed within the polishing station and configured to be selectively moved proximate the polishing pad. The method includes the steps of determining a thickness measurement of the polishing pad and adjusting at least one tool parameter…
Varying conductance out of a process region to control gas flux in an ALD reactor
Granted: March 13, 2007
Patent Number:
7189432
A deposition system includes a process chamber for conducting an ALD process to deposit layers on a substrate. In one embodiment, instead of varying the gas flux on a substrate in the chamber by controlling the flow of gas upstream of the process chamber, the gas flux on the substrate is controlled by controlling the conductance between the process chamber and a lower pressure volume outside the process chamber. The flux of the gas on the substrate varies inversely with the chamber…
Sequential station tool for wet processing of semiconductor wafers
Granted: March 13, 2007
Patent Number:
7189647
Methods and apparatus are provided for processing semiconductor wafers sequentially. Sequential processes employ multi-station processing modules, where particular encompassing wafer processes are divided into sub-processes, each optimized for increasing wafer to wafer uniformity, result quality, and overall wafer throughput. In one example, a copper electroplating module includes separate stations for wetting, initiation, seed layer repair, fill, overburden, reclaim, and rinse.
Barrier first method for single damascene trench applications
Granted: March 6, 2007
Patent Number:
7186648
Methods for forming a diffusion barrier on low aspect features of an integrated circuit include at least three operations. The first operation deposits a barrier material and simultaneously etches a portion of an underlying metal at the bottoms of recessed features of the integrated circuit. The second operation deposits barrier material to provide some minimal coverage over the bottoms of the recessed features. The third operation deposits a metal conductive layer. Controlled etching is…
Method and apparatus for post-CMP cleaning of a semiconductor work piece
Granted: February 27, 2007
Patent Number:
7182673
A method and apparatus are provided for post-CMP cleaning of a semiconductor work piece. The method comprises the steps of subjecting the work piece to a first cleaning composition having one of an acidic pH and a basic pH and subjecting the work piece to a second cleaning composition having an acidic pH, if the first cleaning composition has a basic pH and subjecting the work piece to a second cleaning composition having a basic pH, if the first cleaning composition has an acidic pH.
Methods and apparatus for magnetron sputtering
Granted: February 20, 2007
Patent Number:
7179351
In one embodiment, a magnetron sputtering apparatus forms a closed plasma loop and an open plasma loop within the closed plasma loop. The open plasma loop allows for relatively uniform erosion on the face of a target by broadening the sputtered area of the target. The open plasma loop may be formed and swirled using a rotating magnetic array to average the target erosion.
Dynamic modification of gap fill process characteristics
Granted: February 13, 2007
Patent Number:
7176039
A method for process optimization to extend the utility of the HDP CVD gap fill technique modifies the characteristics of the HDP process (deposition and sputter components) in a dynamic mode in the course of filling a trench with dielectric material. As a result, the amount of dielectric deposited on the sidewall of the trench relative to that deposited at its bottom can be reduced and optimally minimized, thus improving the gap fill capability of the process. The dynamic modification…
Plasma detemplating and silanol capping of porous dielectric films
Granted: February 13, 2007
Patent Number:
7176144
Methods of preparing a low-k dielectric material on a substrate are provided. The methods involve using plasma techniques to remove porogen from a precursor layer comprising porogen and a dielectric matrix and to protect the dielectric matrix with a silanol capping agent, resulting in a low-k dielectric matrix. Porogen removal and silanol capping can occur concurrently or sequentially. If performed sequentially, silanol capping is performed without first exposing the dielectric matrix to…
Adhesion promotion for etch by-products
Granted: February 13, 2007
Patent Number:
7176140
Methods and apparatus for cleaning a semiconductor substrate that significantly reduce the number of particles falling onto the substrate during cleaning by coating all interior surfaces within a processing chamber with an adhesion film that has an increased sticking coefficient for any subsequently arriving etched species to promote a continuous film growth and improve adhesion of such etched species. Due to its increased sticking coefficient, this adhesion film reduces surface mobility…
VLSI fabrication processes for introducing pores into dielectric materials
Granted: January 23, 2007
Patent Number:
7166531
Porous dielectric layers are produced by introducing pores in pre-formed composite dielectric layers. The pores may be produced after the barrier material, the metal or other conductive material is deposited to form a metallization layer. In this manner, the conductive material is provided with a relatively smooth continuous surface on which to deposit.
Film for copper diffusion barrier
Granted: January 16, 2007
Patent Number:
7163889
The present invention provides a low dielectric constant copper diffusion barrier film suitable for use in a semiconductor device and methods for fabricating such a film. Some embodiments of the film are formed of a silicon-based material doped with boron. Other embodiments are formed, at least in part, of boron nitride. Some such embodiments include a moisture barrier film that includes oxygen and/or carbon. Preferred embodiments of the copper diffusion barrier maintain a stable…
Biased Hetch process in deposition-etch-deposition gap fill
Granted: January 16, 2007
Patent Number:
7163896
Biased plasma etch processes incorporating H2 etch chemistries. In particular, high density plasma chemical vapor etch-enhanced (deposition-etch-deposition) gap fill processes incorporating etch chemistries which incorporate hydrogen as the etchant that can effectively fill high aspect ratio gaps while reducing or eliminating dielectric contamination by etchant chemical species.
Localized energy pulse rapid thermal anneal dielectric film densification method
Granted: January 16, 2007
Patent Number:
7163899
A densified dielectric film is formed on a substrate by a process that involves annealing a film deposited on the substrate by application of a localized energy pulse, such as a laser pulse, for example one of about 10 to 100 ns in duration from an excimer laser, that raises the temperature of the film above 1000° C. without raising the substrate temperature sufficiently to modify its properties (e.g., the substrate temperature remains below 550° C. or preferably in many applications…
Adhesion of tungsten nitride films to a silicon surface
Granted: January 9, 2007
Patent Number:
7160802
A process is described that forms a low resistivity connection between a tungsten layer and a silicon surface with high adherence of the tungsten to the silicon. The silicon surface is plasma-cleaned to remove native oxide. A very thin layer (one or more monolayers) of Si—NH2 is formed on the silicon surface, serving as an adhesion layer. A WNx layer is formed over the Si—NH2 layer, using an atomic layer deposition (ALD) process, to serve as a barrier layer. A thick tungsten layer is…
Etch back process approach in dual source plasma reactors
Granted: January 9, 2007
Patent Number:
7160813
A method is disclosed for removing a polysilicon layer from a semiconductor wafer, in which a downstream plasma source is used first to planarize the wafer, removing contours in the polysilicon layer caused by deposition over lithographic features, such as via holes. The planarizing process is followed by exposure to a plasma made by a direct, radio frequency plasma source, which may be in combination with the downstream plasma source, to perform the bulk etching of the polysilicon. The…
Selective refractory metal and nitride capping
Granted: January 2, 2007
Patent Number:
7157798
A method for creating a refractory metal and refractory metal nitride cap effective for reducing copper electromigration and copper diffusion is described. The method includes depositing a refractory metal nucleation layer and nitriding at least the upper portion of the refractory metal layer to form a refractory metal nitride. Methods to reduce and clean the copper lines before refractory metal deposition are also described. Methods to form a thicker refractory metal layer using bulk…
