DYNAMIC STANDARD CELL EXTERNAL PIN METHODOLOGY FOR ROUTABILITY-DRIVEN STANDARD CELL DESIGN AUTOMATION
Granted: December 12, 2024
Application Number:
20240411977
Lattice graph routability modelling mechanisms for standard cells utilizing a trained lattice graph routability model to determine routability metrics for local areas and global net connections in the standard cell. The metrics are applied to influence transistor placement in the standard cell, resulting in standard cell layouts with improved routability. Circuit layout generating processes are also described, in which a layout is formed lacking external pin assignments, and during…
PIN DENSITY-BASED CONGESTION ESTIMATION FOR ROUTABILITY-DRIVEN STANDARD CELL SYNTHESIS
Granted: December 12, 2024
Application Number:
20240411974
Lattice graph routability modelling mechanisms for standard cells utilizing a trained lattice graph routability model to determine routability metrics for local areas and global net connections in the standard cell. The metrics are applied to influence transistor placement in the standard cell, resulting in standard cell layouts with improved routability. Circuit layout generating processes are also described, in which a layout is formed lacking external pin assignments, and during…
VOLTAGE REGULATOR DROOP REDUCTION MECHANISM
Granted: December 5, 2024
Application Number:
20240402740
Power supply circuits in which a supplemental current driver is utilized to boost the current provided by a voltage regulator. The supplementing driver detects operating conditions for providing the supplementary current, and may be trained to provide particular amounts of current in response to particular operation conditions of a circuit load.
DETERMINING OBSTACLE PERCEPTION SAFETY ZONES FOR AUTONOMOUS SYSTEMS AND APPLICATIONS
Granted: December 5, 2024
Application Number:
20240400101
In various examples, systems and methods are disclosed relating to refinement of safety zones and improving evaluation metrics for the perception modules of autonomous and semi-autonomous systems. Example implementations can exclude areas in the state space that are not safety critical, while retaining the areas that are safety-critical. This can be accomplished by leveraging ego maneuver information and conditioning safety zone computations on ego maneuvers. A maneuver-based…
METHOD FOR INTEGRATING A COPPER-GRAPHENE LAMINATE (CGL) IN A MULTILAYER PCB FABRICATION PROCESS
Granted: November 28, 2024
Application Number:
20240397636
Methods for integrating copper-graphene laminate (CGL) in a multilayer PCB fabrication process and the resulting lamination stacks are disclosed. The methods include providing a core and applying a first graphene layer to the surface of the core. The methods further include applying a metal layer to the first graphene layer and applying a second graphene layer to the metal layer. Further, the methods include applying a photoresist layer to the second graphene layer and applying a…
GRAPHENE INTEGRATED CORE AND ASSOCIATED METHODS FOR THERMAL MANAGEMENT WITHIN PRINTED CIRCUIT BOARDS
Granted: November 28, 2024
Application Number:
20240397604
Methods of forming a graphene integrated core for making a printed circuit board (PCB) having enhanced thermal management properties are disclosed. The methods include providing a core body having a core body length and applying a graphene multi-layer to the core body to form a laminated stack, where the graphene multi-layer has a graphene multi-layer length that is shorter than the core body length. At least one conductive layer may be applied to the laminated stack. The graphene…
CONTENTION-FREE DUAL-VOLTAGE LOGIC CELL
Granted: November 28, 2024
Application Number:
20240395293
Mechanisms to mitigate signal race conditions in circuits that utilize multiple voltage domains. The mechanisms are applicable in signal fanout scenarios where leakage becomes problematic to signal timing, such machine memory devices, e.g., volatile single port or multi-port memory devices such as SRAMs (volatile static random access memory) or other bit-storing cell arrangements that include memory cells and a hierarchical bitline structure including local bitlines for subsets of the…
BIDIRECTIONAL MICRORING RESONATOR-BASED PHOTONIC LINK ARCHITECTURE
Granted: November 21, 2024
Application Number:
20240385381
Optical transceiver architecture utilizing micro-ring modulators and micro-ring resonators configured to route resonant wavelengths of light injected into each micro-ring resonator's input port and through port to that micro-ring resonator's drop port and add port, respectively. The micro-ring resonators drop two distinct streams of data modulated onto the same optical wavelength, or two wavelengths separated by an integer number of free spectral ranges coupled into the micro-ring…
SCENE UNDERSTANDING USING LANGUAGE MODELS FOR ROBOTICS SYSTEMS AND APPLICATIONS
Granted: November 21, 2024
Application Number:
20240386733
In various examples, 3D object knowledge can be developed to extract diverse knowledge from large language models, and a part-grounding model can be trained to ground part semantics in terms of local shape features and spatial relations between parts. For example, knowledge that “the opening part of a mug that affords the pouring action is located on the top of the mug body and is often circular” can be grounded by identifying a previously unknown “opening” part based on its…
OBJECT SEGMENTATION USING MACHINE LEARNING FOR AUTONOMOUS SYSTEMS AND APPLICATIONS
Granted: November 21, 2024
Application Number:
20240386586
In various examples, systems and methods are disclosed relating to using neural networks for object detection or instance/semantic segmentation for, without limitation, autonomous or semi-autonomous systems and applications. In some implementations, one or more neural networks receive an image (or other sensor data representation) and a bounding shape corresponding to at least a portion of an object in the image. The bounding shape can include or be labeled with an identifier, class,…
FERROMAGNETIC MATERIAL BASED INTEGRATED INDUCTOR IN SILICON
Granted: November 14, 2024
Application Number:
20240379731
A process for manufacturing inductors for use in integrated circuits includes embedding ferromagnetic material in a bulk silicon substrate, forming a plurality of vias in the bulk silicon substrate such that the vias bracket a volume of the bulk silicon substrate that includes the ferromagnetic material, slicing the bulk silicon substrate to form a silicon wafer, and configuring traces between top metal pads of the vias and between bottom metal pads of the vias to form a continuous path…
SYNTHETIC DATA GENERATION USING VIEWPOINT AUGMENTATION FOR AUTONOMOUS SYSTEMS AND APPLICATIONS
Granted: October 31, 2024
Application Number:
20240362897
In various examples, systems and methods are disclosed relating to synthetic data generation using viewpoint augmentation for autonomous and semi-autonomous systems and applications. One or more circuits can identify a set of sequential images corresponding to a first viewpoint and generate a first transformed image corresponding to a second viewpoint using a first image of the set of sequential images as input to a machine-learning model. The one or more circuits can update the…
Chip Die Substrate with Edge-Mounted Capacitors
Granted: October 3, 2024
Application Number:
20240332223
An integrated circuit die substrate has one or more capacitors attached to an edge surface of the substrate. The substrate has a top surface and a bottom surface, at least one of which includes a die mounting area, and at least one of which includes system interconnect terminals. A substrate edge surface is disposed along a peripheral end of the substrate and is oriented substantially orthogonally to the top and bottom surfaces. A pair of conductive edge terminals is disposed on the…
ON DIE CURRENT SINK CIRCUIT FOR OVERSHOOT MITIGATION
Granted: September 26, 2024
Application Number:
20240322559
An integrated circuit that includes multiple power rails with dummy loads configured on at least some of the power rails. The dummy loads are activated in response to a voltage overshoot condition on regions of the power rails at which the dummy loads are located. The dummy loads may be substituted for decoupling capacitors or other active cells at particular regions of the power rails.
DECIDER NETWORKS FOR REACTIVE DECISION-MAKING FOR ROBOTIC SYSTEMS AND APPLICATIONS
Granted: September 26, 2024
Application Number:
20240319713
In various examples, systems and methods are disclosed relating to decider networks for reactive decision-making, including for control of robotic systems. The decider networks can allow robotic systems to operate more collaboratively, such as by allowing the robotic systems to more frequently process and react to dynamic states of the environment and objects in the environment, such as to change decisions and/or paths of decision execution responsive to dynamic changes in logical…
DATA AUGMENTATION FOR MODEL TRAINING IN AUTONOMOUS SYSTEMS AND APPLICATIONS
Granted: September 19, 2024
Application Number:
20240312123
In various examples, systems and methods are disclosed that relate to data augmentation for training/updating perception models in autonomous or semi-autonomous systems and applications. For example, a system may receive data associated with a set of frames that are captured using a plurality of cameras positioned in fixed relation relative to the machine; generate a panoramic view based at least on the set of frames; provide data associated with the panoramic view to a model to cause…
PROCESSOR ARCHITECTURE FOR OPTIMIZED PARALLELIZED SEARCH
Granted: September 12, 2024
Application Number:
20240303085
Systems and methods in accordance with the present disclosure can implement a parallel processing system, such as a graphics processing unit (GPU)-based system, to generate solutions to complex computational problems. Aspects of this technical solution can retrieve a plurality of solutions each representing a plurality of values in a multi-dimensional space, allocate, to one or more processing units associated with the one or more circuits and having a parallelized configuration, one or…
LOGIC CELL PLACEMENT MECHANISMS FOR IMPROVED CLOCK ON-CHIP VARIATION
Granted: September 5, 2024
Application Number:
20240296274
Mechanisms to place flip-flops and other synchronous logic cells in a circuit layout in a clock on-chip variation-aware, predetermined order based on analysis of the clock gating, connectivity, and logic depth of the unplaced netlist. The resulting placements enable clock trees having a regular structure leading to improvements in clock on-chip variation, timing, and clock power.
SYSTEM FOR IMPLEMENTING MUTABLE DEVICE OWNERSHIP TRANSFER (DOT) OF A DEVICE
Granted: August 22, 2024
Application Number:
20240281514
Systems and methods are described herein for implementing a mutable device ownership transfer (DOT) of a device. An example system receives a request from a first customer to record a mutable DOT of a device using a First Customer Authentication Key (FCAK); receives the FCAK from the first customer in response to receiving the request; determines whether the device is capable of recording the mutable DOT; and installs, using a DOT circuitry, the FCAK in a non-volatile memory of a Root of…
TRANSIENT CURRENT-MODE SIGNALING SCHEME FOR ON-CHIP INTERCONNECT FABRICS
Granted: August 8, 2024
Application Number:
20240264625
Circuits that include one or more transmission lines to propagate a signal through a serially-arranged plurality of repeaters, and one or more control circuits to propagate control pulses to the repeaters, wherein a timing and duration of the control pulses is configured to operate the repeaters in current-mode signaling (CMS) mode during a state transition of the signal at the repeaters and to operate the repeaters in voltage-mode signaling (VMS) mode otherwise.
