DIGITALLY CONTROLLED UNIFIED RECEIVER FOR MULTI-RANK SYSTEM
Granted: November 2, 2023
Application Number:
20230353155
A multi-rank circuit system includes multiple transmitters each switchably coupled to a first end of a shared input/output (IO) channel and a unified receiver coupled to a second end of the shared IO channel. The unified receiver is coupled to apply a preconfigured analog reference voltage to set a differential output of the unified receiver, and further configured to apply a variable digital code to adjust the differential output according to a particular one of the transmitters that is…
LOOK AHEAD SWITCHING CIRCUIT FOR A MULTI-RANK SYSTEM
Granted: November 2, 2023
Application Number:
20230352081
A multi-rank circuit system utilizing a shared IO channel includes a first stage of multiple selectors coupled to input multiple digital busses, and a second stage including one or more selectors coupled to receive outputs of the first stage of selectors and to individually select one of the outputs of the first stage of selectors to one or more control circuits for IO circuits of the ranks. The system switches one of the ranks to be an active rank on the shared IO channel, and operates…
TRAINING AND CONFIGURATION OF REFERENCE VOLTAGE GENERATORS IN A MULTI-RANK CIRCUIT SYSTEM
Granted: November 2, 2023
Application Number:
20230352078
The differential voltage output from a first reference voltage generator of a multi-rank circuit is trained on multiple ranks of the multi-rank circuit. Multiple local reference voltage generators are trained to generate reference voltages for communication on the individual ranks, where the reference voltages output by the local reference voltage generators fall within a range of the differential voltage output.
DISTRIBUTED GLOBAL AND LOCAL REFERENCE VOLTAGE GENERATION
Granted: November 2, 2023
Application Number:
20230352077
A method includes generating a differential voltage from a first reference voltage generator; receiving the differential voltage at a second reference voltage generator; dividing the differential voltage at the second reference voltage generator into multiple available reference voltage levels; and selecting one of the available reference voltage levels to apply to a circuit.
MULTI-RANK RECEIVER
Granted: November 2, 2023
Application Number:
20230352067
A multi-rank system includes multiple circuit ranks communicating over a common data line to multiple data receivers, each corresponding to one or more of the ranks and each having a corresponding reference voltage generator and clock timing adjustment circuit, such that a rank to communicate on the shared data line is switched without reconfiguring outputs of either the reference voltage generators or the clock timing adjustment circuits.
Three Dimensional Circuit Mounting Structures
Granted: October 19, 2023
Application Number:
20230337350
A circuit board includes chip die mounted on a three dimensional rectangular structure, a three dimensional triangular prism structure, or a combination thereof. A ball grid array for the chip die mounted on any such three dimensional structure is interposed between the three dimensional structure and the circuit board itself.
GENERATIVE SELF-SUPERVISED LEARNING TO TRANSFORM CIRCUIT NETLISTS
Granted: October 19, 2023
Application Number:
20230334215
Self-supervised machine learning is applied to combinational gate sizing based on an input circuit netlist. A transformer neural network architecture is disclosed to select gate sizes along paths of the network between primary inputs/outputs and/or sequential logic elements. The gate size selections may be optimized along dimensions such as path delay, path power consumption, and path circuit area.
CONTROL OF STORAGE ALIASING VIA AUTOMATIC APPLICATION OF ARTIFICIAL DEPENDENCES DURING PROGRAM COMPILATION
Granted: October 19, 2023
Application Number:
20230333825
In various examples, systems and methods are disclosed relating to aliasing control of program variables in storage via automatic application of artificial dependences during program compilation. In some implementations, a system can include a detector to automatically detect a pattern, based at least on a structure of data flow in a source program, indicative of sequences of dependent operations, where the sequences are independent from one another. The system can determine a storage…
HARDWARE-EFFICIENT PAM-3 ENCODER AND DECODER
Granted: October 12, 2023
Application Number:
20230327924
Data bits are encoded in an eleven bit seven pulse amplitude modulated three-level (PAM-3) symbol format on a plurality of data channels and two auxiliary data channels, and one or more of a cyclic redundancy check (CRC) value, a poison value, and a severity value are encoded as PAM-3 symbols on an error correction channel.
HARDWARE-EFFICIENT PAM-3 ENCODER AND DECODER
Granted: September 21, 2023
Application Number:
20230297466
Data bits are encoded in an eleven bit seven pulse amplitude modulated three-level (PAM-3) symbol format on a plurality of data channels and two auxiliary data channels, and one or more of a cyclic redundancy check (CRC) value, a poison value, and a severity value are encoded as PAM-3 symbols on an error correction channel.
HARDWARE-EFFICIENT PAM-3 ENCODER AND DECODER
Granted: September 21, 2023
Application Number:
20230297466
Data bits are encoded in an eleven bit seven pulse amplitude modulated three-level (PAM-3) symbol format on a plurality of data channels and two auxiliary data channels, and one or more of a cyclic redundancy check (CRC) value, a poison value, and a severity value are encoded as PAM-3 symbols on an error correction channel.
SYSTEM AND METHOD FOR GPU-INITIATED COMMUNICATION
Granted: August 31, 2023
Application Number:
20230276422
A computer based system and method for sending data packets over a data network may include: preparing data packets and packet descriptors on one or more graphical processing units (GPUs); associating packets with a packet descriptor, which may determine a desired transmission time of the packets associated with that descriptor; receiving an indication of a clock time; and physically transmitting packets via an output interface, at a clock time corresponding to the desired transmission…
SYSTEM AND METHOD FOR GPU-INITIATED COMMUNICATION
Granted: August 31, 2023
Application Number:
20230276301
A computer based system and method for sending data packets over a data network may include: preparing data packets and packet descriptors on one or more graphical processing units (GPUs); associating packets with a packet descriptor, which may determine a desired transmission time of the packets associated with that descriptor; receiving an indication of a clock time; and physically transmitting packets via an output interface, at a clock time corresponding to the desired transmission…
CIRCUIT STRUCTURES TO MEASURE FLIP-FLOP TIMING CHARACTERISTICS
Granted: August 31, 2023
Application Number:
20230275572
A ring oscillator circuit with a frequency that is sensitive to the timing of a clock-to-Q (clk2Q) propagation delay of one or more flip-flops utilized in the ring oscillator. The clock2Q is the delay between the clock signal arriving at the clock pin on the flop and the Q output reflecting the state of the input data signal to the flop. Clk2q delay measurements are made based on measurement of the ring oscillator frequency, leading to more accurate estimates of clk2Q for different types…
Adaptive Pixel Sampling Order for Temporally Dense Rendering
Granted: August 24, 2023
Application Number:
20230269391
A method dynamically selects one of a first sampling order and a second sampling order for a ray trace of pixels in a tile where the selection is based on a motion vector for the tile. The sampling order may be a bowtie pattern or an hourglass pattern.
CMOS SIGNALING FRONT END FOR EXTRA SHORT REACH LINKS
Granted: August 24, 2023
Application Number:
20230269119
A transceiver circuit includes a receiver front end utilizing a ring oscillator, and a transmitter front end utilizing a pass-gate circuit in a first feedback path across a last-stage driver circuit. The transceiver circuit provides low impedance at low frequency and high impedance at high frequency, and desirable peaking behavior.
KEEPER-FREE VOLATILE MEMORY SYSTEM
Granted: August 24, 2023
Application Number:
20230267992
A static random access memory (SRAM) or other bit-storing cell arrangement includes memory cells and a hierarchical bitline structure including local bitlines for subsets of the memory banks and a global bitline spanning the subsets. A keeper circuit for the global bitline is replaced by bias circuitry on output transistors of the memory cells.
TRANSCEIVER SYSTEM WITH END-TO-END RELIABILITY AND ORDERING PROTOCOLS
Granted: August 17, 2023
Application Number:
20230261794
Packet flows between a transmitter and a receiver in an unreliable and unordered switched packet network may be established as a result of receiving a second packet comprising a second memory operation on a memory address. The transmission of memory load command packets followed by memory store command packets in the packet flow may be serialized, and a synchronization operation may be executed between the transmitter and the receiver when a packet count at the receiver satisfies a…
Denoising ATAC-Seq Data With Deep Learning
Granted: August 3, 2023
Application Number:
20230245718
The present invention provides methods, systems, computer program products that use deep learning with neural networks to denoise ATAC-seq datasets. The methods, systems, and programs provide for increased efficiency, accuracy, and speed in identifying genomic sites of chromatin accessibility in a wide range of tissue and cell types.
Simultaneous Bi-directional Hybrid Transceiver for Single-Ended Voltage Mode Signaling
Granted: August 3, 2023
Application Number:
20230246661
A simultaneous bi-directional (SBD) transceiver includes a main transmit driver, a replica transmit driver, and a series-series-bridged (SSB) tri-impedance network. A pre-driver stage includes parallel delay paths for the main transmit driver and the replica transmit driver, enabling the delay for signals received by the main transmit driver and the replica transmit driver to be independently configured.
