LEVEL-CONVERSION CIRCUITS FOR SIGNALING ACROSS VOLTAGE DOMAINS
Granted: January 25, 2024
Application Number:
20240030917
Stacked voltage domain level shifting circuits for shifting signals low-to-high or high-to-low include a storage cell and control drivers powered by a mid-range supply rail of the stacked voltage domain level shifting circuit, wherein the control drivers are coupled to drive common-source configured devices coupled to storage nodes of the storage cell.
LEVEL-CONVERSION CIRCUITS FOR SIGNALING ACROSS VOLTAGE DOMAINS
Granted: January 25, 2024
Application Number:
20240030916
A level-shifting circuits utilizing storage cells for shifting signals low-to-high or high-to-low include control drivers with moving supply voltages. The moving supply voltages may power positive or negative supply terminals of the control drivers. The control drivers drive gates of common-source configured devices coupled to storage nodes of the storage cell.
LEVEL-CONVERSION CIRCUITS FOR SIGNALING ACROSS VOLTAGE DOMAINS
Granted: January 25, 2024
Application Number:
20240030918
Stacked voltage domain level shifting circuits for shifting signals low-to-high or high-to-low include a storage cell powered by a mid-range supply rail of the stacked voltage domain level shifting circuit, and control drivers powered by moving supply voltages generated by the storage cell, wherein the control drivers coupled to drive gates of common-source configured devices coupled to storage nodes of the storage cell.
LEVEL-CONVERSION CIRCUITS FOR SIGNALING ACROSS VOLTAGE DOMAINS
Granted: January 25, 2024
Application Number:
20240030917
Stacked voltage domain level shifting circuits for shifting signals low-to-high or high-to-low include a storage cell and control drivers powered by a mid-range supply rail of the stacked voltage domain level shifting circuit, wherein the control drivers are coupled to drive common-source configured devices coupled to storage nodes of the storage cell.
LEVEL-CONVERSION CIRCUITS FOR SIGNALING ACROSS VOLTAGE DOMAINS
Granted: January 25, 2024
Application Number:
20240030916
A level-shifting circuits utilizing storage cells for shifting signals low-to-high or high-to-low include control drivers with moving supply voltages. The moving supply voltages may power positive or negative supply terminals of the control drivers. The control drivers drive gates of common-source configured devices coupled to storage nodes of the storage cell.
LARGE SCALE MASK OPTIMIZATION WITH CONVOLUTIONAL FOURIER NEURAL OPERATOR AND LITHO-GUIDED SELF LEARNING
Granted: January 11, 2024
Application Number:
20240013033
A circuit mask optimizer utilizes a Convolutional Fourier Neural Operator (CFNO) to efficiently learn layout tile dependencies, enabling stitch-less largescale mask optimization with limited intervention of legacy tools. Litho-guided self training via a trained machine learning model provides non-convex optimization, enabling iterative model and dataset refinements at a substantial performance improvement over conventional solutions.
LARGE SCALE MASK OPTIMIZATION WITH CONVOLUTIONAL FOURIER NEURAL OPERATOR AND LITHO-GUIDED SELF LEARNING
Granted: January 11, 2024
Application Number:
20240013033
A circuit mask optimizer utilizes a Convolutional Fourier Neural Operator (CFNO) to efficiently learn layout tile dependencies, enabling stitch-less largescale mask optimization with limited intervention of legacy tools. Litho-guided self training via a trained machine learning model provides non-convex optimization, enabling iterative model and dataset refinements at a substantial performance improvement over conventional solutions.
REDUCING LEVEL OF DETAIL OF A POLYGON MESH TO DECREASE A COMPLEXITY OF RENDERED GEOMETRY WITHIN A SCENE
Granted: December 28, 2023
Application Number:
20230419611
A method, computer readable medium, and system are disclosed for overlaying a cell onto a polygon meshlet. The polygon meshlet may include a grouping of multiple geometric shapes such as triangles, and the cell may include a square-shaped boundary. Additionally, every polygon (e.g., a triangle or other geometric shape) within the polygon meshlet that has at least one edge fully inside the cell is removed to create an intermediate meshlet. A selected vertex is determined from all vertices…
HARDWARE-EFFICIENT PAM-3 ENCODER AND DECODER
Granted: December 28, 2023
Application Number:
20230418705
A transceiver configured to communicate a burst of data bits and meta-data bits for the data bits includes data channels, auxiliary data channels, and at least one error correction channel. The transceiver includes an encoder that applies 11b7s encoding to a first number of the data bits to generate first PAM-3 symbols on some or all of the communication channels, and that applies 3b2s encoding to a second number of the data bits to generate second PAM-3 symbols on at least some of the…
STAGGERED DUAL-SIDE MULTI-CHIP INTERCONNECT
Granted: December 21, 2023
Application Number:
20230411365
Layout techniques for circuits on substrates are disclosed that address the multivariate problem of minimizing routing distances for high-speed I/O pins between circuits while simultaneously providing for the rapid provision of transient power demands to the circuits. The layout techniques may also enable improved thermal management for the circuits.
GLOBAL CONTEXT VISION TRANSFORMER
Granted: December 7, 2023
Application Number:
20230394781
Vision transformers are deep learning models that employ a self-attention mechanism to obtain feature representations for an input image. To date, the configuration of vision transformers has limited the self-attention computation to a local window of the input image, such that short-range dependencies are modeled in the output. The present disclosure provides a vision transformer that captures global context, and that is therefore able to model long-range dependencies in its output.
DEEP LEARNING-BASED WIRELESS COMMUNICATION SYNCHRONIZATION STRUCTURES
Granted: November 23, 2023
Application Number:
20230379746
Neural network-based structures for action user equipment device detection, estimation of time-of-arrival, and estimation of carrier frequency offset utilized with the narrowband physical random-access channel of wireless communication systems. The structure includes a neural network to generate predictions of active user equipment devices, and a twin neural network to generate time-of-arrival predictions for signals from the user equipment devices and carrier frequency offset…
MULTI-DOMAIN GENERATIVE ADVERSARIAL NETWORKS FOR SYNTHETIC DATA GENERATION
Granted: November 23, 2023
Application Number:
20230377324
In various examples, systems and methods are disclosed relating to multi-domain generative adversarial networks with learned warp fields. Input data can be generated according to a noise function and provided as input to a generative machine-learning model. The generative machine-learning model can determine a plurality of output images each corresponding to one of a respective plurality of image domains. The generative machine-learning model can include at least one layer to generate a…
POWER REGULATOR INTERFACES FOR INTEGRATED CIRCUITS
Granted: November 9, 2023
Application Number:
20230363093
A circuit system includes an integrated circuit package mounted on a first side of a printed circuit board and a power regulator connected to power terminals of the integrated circuit package through a cutout in the printed circuit board. The power regulator draws power from the printed circuit board by way of side pins around a periphery of the cutout.
POWER REGULATOR INTERFACES FOR INTEGRATED CIRCUITS
Granted: November 9, 2023
Application Number:
20230363085
A circuit system includes an integrated circuit package mounted on a first side of a printed circuit board and a power regulator connected to power terminals of the integrated circuit package through a cutout in the printed circuit board. The power regulator draws power from the printed circuit board by way of connections on a shelf region extending beyond an area of the cutout.
MULTI-RANK RECEIVER
Granted: November 2, 2023
Application Number:
20230352067
A multi-rank system includes multiple circuit ranks communicating over a common data line to multiple data receivers, each corresponding to one or more of the ranks and each having a corresponding reference voltage generator and clock timing adjustment circuit, such that a rank to communicate on the shared data line is switched without reconfiguring outputs of either the reference voltage generators or the clock timing adjustment circuits.
DIGITALLY CONTROLLED UNIFIED RECEIVER FOR MULTI-RANK SYSTEM
Granted: November 2, 2023
Application Number:
20230353155
A multi-rank circuit system includes multiple transmitters each switchably coupled to a first end of a shared input/output (IO) channel and a unified receiver coupled to a second end of the shared IO channel. The unified receiver is coupled to apply a preconfigured analog reference voltage to set a differential output of the unified receiver, and further configured to apply a variable digital code to adjust the differential output according to a particular one of the transmitters that is…
LOOK AHEAD SWITCHING CIRCUIT FOR A MULTI-RANK SYSTEM
Granted: November 2, 2023
Application Number:
20230352081
A multi-rank circuit system utilizing a shared IO channel includes a first stage of multiple selectors coupled to input multiple digital busses, and a second stage including one or more selectors coupled to receive outputs of the first stage of selectors and to individually select one of the outputs of the first stage of selectors to one or more control circuits for IO circuits of the ranks. The system switches one of the ranks to be an active rank on the shared IO channel, and operates…
TRAINING AND CONFIGURATION OF REFERENCE VOLTAGE GENERATORS IN A MULTI-RANK CIRCUIT SYSTEM
Granted: November 2, 2023
Application Number:
20230352078
The differential voltage output from a first reference voltage generator of a multi-rank circuit is trained on multiple ranks of the multi-rank circuit. Multiple local reference voltage generators are trained to generate reference voltages for communication on the individual ranks, where the reference voltages output by the local reference voltage generators fall within a range of the differential voltage output.
DISTRIBUTED GLOBAL AND LOCAL REFERENCE VOLTAGE GENERATION
Granted: November 2, 2023
Application Number:
20230352077
A method includes generating a differential voltage from a first reference voltage generator; receiving the differential voltage at a second reference voltage generator; dividing the differential voltage at the second reference voltage generator into multiple available reference voltage levels; and selecting one of the available reference voltage levels to apply to a circuit.
