SYSTEM AND METHODS FOR HARDWARE-SOFTWARE COOPERATIVE PIPELINE ERROR DETECTION
Granted: July 2, 2020
Application Number:
20200210276
An error reporting system utilizes a parity checker to receive data results from execution of an original instruction and a parity bit for the data. A decoder receives an error correcting code (ECC) for data resulting from execution of a shadow instruction of the original instruction, and data error correction is initiated on the original instruction result on condition of a mismatch between the parity bit and the original instruction result, and the decoder asserting a correctable error…
USE OF STASHING BUFFERS TO IMPROVE THE EFFICIENCY OF CROSSBAR SWITCHES
Granted: June 4, 2020
Application Number:
20200177521
A switch architecture enables ports to stash packets in unused buffers on other ports, exploiting excess internal bandwidth that may exist, for example, in a tiled switch. This architecture leverages unused port buffer memory to improve features such as congestion handling and error recovery.
DEEP LEARNING BASED IDENTIFICATION OF DIFFICULT TO TEST NODES
Granted: May 14, 2020
Application Number:
20200151289
Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.
Deep Learning Testability Analysis with Graph Convolutional Networks
Granted: May 14, 2020
Application Number:
20200151288
Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.
SCALABLE MULTI-DIE DEEP LEARNING SYSTEM
Granted: March 12, 2020
Application Number:
20200082246
A distributed deep neural net (DNN) utilizing a distributed, tile-based architecture implemented on a semiconductor package. The package includes multiple chips, each with a central processing element, a global memory buffer, and processing elements. Each processing element includes a weight buffer, an activation buffer, and multiply-accumulate units to combine, in parallel, the weight values and the activation values.
CONVERGENCE AMONG CONCURRENTLY EXECUTING THREADS
Granted: March 12, 2020
Application Number:
20200081748
Convergence of threads executing common code sections is facilitated using instructions inserted at strategic locations in computer code sections. The inserted instructions enable the threads in a warp or other group to cooperate with a thread scheduler to promote thread convergence.
MAXIMUM TRANSITION AVOIDANCE (MTA) ENCODING
Granted: December 19, 2019
Application Number:
20190386677
A PAM-4 communication process divides a full burst of raw data into two half bursts, extracts a bit from each half burst and communicating the extracted bit on a DBI line, and encodes the remaining bits of the half burst to avoid maximum transitions between PAM-4 symbols on a data line.
CAMERA BLOCKAGE DETECTION FOR AUTONOMOUS DRIVING SYSTEMS
Granted: May 9, 2019
Application Number:
20190138821
System and methods for detecting blockages in images are described. A method may include receiving a plurality of images captured by a camera installed on a vehicle. The method may include identifying one or more candidate blocked regions in the plurality of images. Each of the candidate blocked regions may contain image data caused by blockages in the camera's field-of-view. The method may further include assigning blockage scores to the one or more candidate blocked regions based on…
PATH PLANNING FOR VIRTUAL REALITY LOCOMOTION
Granted: January 10, 2019
Application Number:
20190012832
A method, computer readable medium, and system are disclosed for computing a path for a user to move along within a physical space while viewing a virtual environment in a virtual reality system. A path for a user to physically move along through a virtual environment is determined based on waypoints and at least one characteristic of the physical environment within which the user is positioned, position data for the user is received indicating whether and how much a current path taken…
PCIE TRAFFIC TRACKING HARDWARE IN A UNIFIED VIRTUAL MEMORY SYSTEM
Granted: December 28, 2017
Application Number:
20170371822
Techniques are disclosed for tracking memory page accesses in a unified virtual memory system. An access tracking unit detects a memory page access generated by a first processor for accessing a memory page in a memory system of a second processor. The access tracking unit determines whether a cache memory includes an entry for the memory page. If so, then the access tracking unit increments an associated access counter. Otherwise, the access tracking unit attempts to find an unused…
MICROCONTROLLER FOR MEMORY MANAGEMENT UNIT
Granted: December 28, 2017
Application Number:
20170371802
One embodiment of the present invention includes a microcontroller coupled to a memory management unit (MMU). The MMU is coupled to a page table included in a physical memory, and the microcontroller is configured to perform one or more virtual memory operations associated with the physical memory and the page table. In operation, the microcontroller receives a page fault generated by the MMU in response to an invalid memory access via a virtual memory address. To remedy such a page…
FAULT BUFFER FOR RESOLVING PAGE FAULTS IN UNIFIED VIRTUAL MEMORY SYSTEM
Granted: November 16, 2017
Application Number:
20170329717
A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the…
FAULT BUFFER FOR TRACKING PAGE FAULTS IN UNIFIED VIRTUAL MEMORY SYSTEM
Granted: October 5, 2017
Application Number:
20170286198
A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the…
NEAR-EYE MICROLENS ARRAY DISPLAYS
Granted: September 21, 2017
Application Number:
20170269358
In embodiments of the invention, an apparatus may include a display comprising a plurality of pixels and a computer system coupled with the display and operable to instruct the display to display images. The apparatus may further include a microlens array located adjacent to the display and comprising a plurality of microlenses, wherein the microlens array is operable to produce a light field by altering light emitted by the display to simulate an object that is in focus to an observer…
PERCEPTUALLY-BASED FOVEATED RENDERING USING A CONTRAST-ENHANCING FILTER
Granted: September 14, 2017
Application Number:
20170263046
A method, computer readable medium, and system are disclosed for rendering images utilizing a foveated rendering algorithm with post-process filtering to enhance a contrast of the foveated image. The method includes the step of receiving a three-dimensional scene, rendering the 3D scene according to a foveated rendering algorithm to generate a foveated image, and filtering the foveated image using a contrast-enhancing filter to generate a filtered foveated image. The foveated rendering…
COMMON POINTERS IN UNIFIED VIRTUAL MEMORY SYSTEM
Granted: August 31, 2017
Application Number:
20170249254
A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the…
METHOD AND SYSTEM FOR INTERPOLATING BASE AND DELTA VALUES OF ASSOCIATED TILES IN AN IMAGE
Granted: August 17, 2017
Application Number:
20170237997
A method for performing image decompression. The method includes identifying a pixel in an image, wherein the image comprises a plurality of tiles including color data that is displayed by a plurality of pixels, wherein each tile is associated with a base value, a delta value, and a plurality of indices. One or more tiles associated with the pixel are identified. An interpolated base is determined by interpolating decompressed bases of the one or more tiles. An interpolated delta is…
MANAGING DEFERRED CONTEXTS IN A CACHE TILING ARCHITECTURE
Granted: July 20, 2017
Application Number:
20170206623
A method for managing bind-render-target commands in a tile-based architecture. The method includes receiving a requested set of bound render targets and a draw command. The method also includes, upon receiving the draw command, determining whether a current set of bound render targets includes each of the render targets identified in the requested set. The method further includes, if the current set does not include each render target identified in the requested set, then issuing a…
MIGRATION SCHEME FOR UNIFIED VIRTUAL MEMORY SYSTEM
Granted: June 29, 2017
Application Number:
20170185526
A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the…
Hybrid Parallel Decoder Techniques
Granted: May 25, 2017
Application Number:
20170150181
Decoder techniques in accordance with embodiment of the present technology include partially decoding a compressed file on a serial based processing unit to find offsets of each of a plurality of entropy data blocks. The compressed file and offset for each of the plurality of entropy encoded data blocks are transferred to a parallel based processing unit. Thereafter, the compressed file is at least partially decoded on the parallel based processing unit using the offset for each of the…
