REFERENCE NOISE COMPENSATION FOR SINGLE-ENDED SIGNALING
Granted: March 18, 2021
Application Number:
20210083836
A receiver circuit includes a clock lane propagating a clock signal. A self-sampled clock applies a delayed version of the clock signal to the clock signal and compensation logic controls an amount of delay of the delayed version of the clock, based on a reference voltage offset (difference) between the receiver and a transmitter. The delayed version of the clock is centered on one unit interval of the clock. An offset correction based on a clock duty cycle error is applied to data…
PACKAGE LEVEL POWER GATING
Granted: February 11, 2021
Application Number:
20210043574
A die package is disclosed through which power domains within the chip may be isolated by removing vias within the package substrate, rather than power gating. Multiple substrate options may be configured without specific vias. This eliminates the need to design power gating circuitry into the die, freeing up that die area for more functional logic. The solution allows the die package to retain the same pinout for use by PCB designers, regardless of which power domains are gated.
OPTIMIZING SOFTWARE-DIRECTED INSTRUCTION REPLICATION FOR GPU ERROR DETECTION
Granted: January 7, 2021
Application Number:
20210004235
A thread execution method in a processor includes executing original instructions of a first thread in a first execution lane of the processor, and interleaving execution of duplicated instructions of the first thread with execution of original instructions of a second thread in a second execution lane of the processor.
CAMERA BLOCKAGE DETECTION FOR AUTONOMOUS DRIVING SYSTEMS
Granted: December 3, 2020
Application Number:
20200380269
Systems and methods for detecting blockages in images are described. An example method may include receiving a plurality of images captured by a camera installed on an apparatus. The method may include identifying one or more candidate blocked regions in the plurality of images. Each of the candidate blocked regions may contain image data caused by blockages in the camera's field-of-view. The method may further include assigning scores to the one or more candidate blocked regions based…
SCALABLE LIGHT-WEIGHT PROTOCOLS FOR WIRE-SPEED PACKET ORDERING
Granted: November 26, 2020
Application Number:
20200374594
A communication method between a source device and a target device utilizes speculative connection setup between the source device and the target device, target-device-side packet ordering, and fine-grained ordering to remove packet dependencies.
SCALABLE LIGHT-WEIGHT PROTOCOLS FOR WIRE-SPEED PACKET ORDERING
Granted: November 26, 2020
Application Number:
20200374593
A communication method between a source device and a target device utilizes speculative connection setup between the source device and the target device, target-device-side packet ordering, and fine-grained ordering to remove packet dependencies.
SEQUENCE VARIATION DETECTION USING DEEP LEARNING
Granted: November 19, 2020
Application Number:
20200365234
The present disclosure provides methods, systems, and computer program products that use embeddings of candidate variation information and deep learning models to accurately and efficiently detect variations in biopolymer sequencing data, particularly suboptimal sequencing data.
CLOCK DATA RECOVERY CONVERGENCE USING SIGNED TIMING INJECTION
Granted: October 22, 2020
Application Number:
20200336286
A system for data and clock recovery includes a timing error detector, a phase detector, and a phase increment injector. The phase increment injector may be used to determine an increment to affect an output of the phase detector or a clocking element. A sign of the increment is determined from a sign or direction of an accumulated version of a clock and data recovery gradient value.
IR DROP PREDICTION WITH MAXIMUM CONVOLUTIONAL NEURAL NETWORK
Granted: October 15, 2020
Application Number:
20200327417
IR drop predictions are obtained using a maximum convolutional neural network. A circuit structure is partitioned into a grid. For cells of the circuit structure in sub-intervals of a clock period, power consumption of the cell is amortized into a set of grid tiles that include portions of the cell, thus forming a set of power maps. The power maps are applied to a neural network to generate IR drop predictions for the circuit structure.
Adaptive Pixel Sampling Order for Temporally Dense Rendering
Granted: October 1, 2020
Application Number:
20200314442
A method dynamically selects one of a first sampling order and a second sampling order for a ray trace of pixels in a tile where the selection is based on a motion vector for the tile. The sampling order may be a bowtie pattern or an hourglass pattern.
RECONSTRUCTION FOR TEMPORALLY DENSE RAY TRACE RENDERING
Granted: October 1, 2020
Application Number:
20200312010
A method dynamically selects one of a first sampling order and a second sampling order for a ray trace of pixels in a tile where the selection is based on a motion vector for the tile. The sampling order may be a bowtie pattern or an hourglass pattern. Subframes generated based on the sampling order are communicated over a bus along with motion vectors for tiles of the subframes.
EFFICIENT NEURAL NETWORK ACCELERATOR DATAFLOWS
Granted: September 17, 2020
Application Number:
20200293867
A distributed deep neural net (DNN) utilizing a distributed, tile-based architecture includes multiple chips, each with a central processing element, a global memory buffer, and a plurality of additional processing elements. Each additional processing element includes a weight buffer, an activation buffer, and vector multiply-accumulate units to combine, in parallel, the weight values and the activation values using stationary data flows.
GENETIC MUTATION DETECTION USING DEEP LEARNING
Granted: September 10, 2020
Application Number:
20200286587
The present disclosure provides methods, systems, and computer program products that use deep learning models to classify candidate mutations detected in sequencing data, particularly suboptimal sequencing data. The methods, systems, and programs provide for increased efficiency, accuracy, and speed in identifying mutations from a wide range of sequencing data.
SWITCHED LOW-DROPOUT VOLTAGE REGULATOR
Granted: August 20, 2020
Application Number:
20200264642
High-resolution switched digital regulators are disclosed having fast cross corner and variable temperature response, with constrained ripple. The strength of the power transistors utilized by the regulator are adjusted to control the current delivered to the load. The regulators utilize a slow control loop in parallel with a primary fast switching loop. The slow loop uses the switching signal of the primary loop to estimate the load current and set the power transistor size accordingly.
Denoising ATAC-Seq Data With Deep Learning
Granted: July 2, 2020
Application Number:
20200211674
The present invention provides methods, systems, computer program products that use deep learning with neural networks to denoise ATAC-seq datasets. The methods, systems, and programs provide for increased efficiency, accuracy, and speed in identifying genomic sites of chromatin accessibility in a wide range of tissue and cell types.
SYSTEM AND METHODS FOR HARDWARE-SOFTWARE COOPERATIVE PIPELINE ERROR DETECTION
Granted: July 2, 2020
Application Number:
20200210276
An error reporting system utilizes a parity checker to receive data results from execution of an original instruction and a parity bit for the data. A decoder receives an error correcting code (ECC) for data resulting from execution of a shadow instruction of the original instruction, and data error correction is initiated on the original instruction result on condition of a mismatch between the parity bit and the original instruction result, and the decoder asserting a correctable error…
USE OF STASHING BUFFERS TO IMPROVE THE EFFICIENCY OF CROSSBAR SWITCHES
Granted: June 4, 2020
Application Number:
20200177521
A switch architecture enables ports to stash packets in unused buffers on other ports, exploiting excess internal bandwidth that may exist, for example, in a tiled switch. This architecture leverages unused port buffer memory to improve features such as congestion handling and error recovery.
DEEP LEARNING BASED IDENTIFICATION OF DIFFICULT TO TEST NODES
Granted: May 14, 2020
Application Number:
20200151289
Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.
Deep Learning Testability Analysis with Graph Convolutional Networks
Granted: May 14, 2020
Application Number:
20200151288
Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.
SCALABLE MULTI-DIE DEEP LEARNING SYSTEM
Granted: March 12, 2020
Application Number:
20200082246
A distributed deep neural net (DNN) utilizing a distributed, tile-based architecture implemented on a semiconductor package. The package includes multiple chips, each with a central processing element, a global memory buffer, and processing elements. Each processing element includes a weight buffer, an activation buffer, and multiply-accumulate units to combine, in parallel, the weight values and the activation values.
