PROTOCOL FOR MEMORY POWER-MODE CONTROL
Granted: November 14, 2013
Application Number:
20130305074
In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response…
RECEIVER CLOCK TEST CIRCUITRY AND RELATED METHODS AND APPARATUSES
Granted: November 7, 2013
Application Number:
20130294490
An integrated circuit includes a plurality of receivers, each having a clock and data recovery circuit. A first local clock recovery circuit in a first receiver can be caused to produce a test clock which simulates a condition to be tested, and while a second receiver in the plurality of receivers that includes a second local clock recovery circuit is caused to use the test clock in place of the reference clock while receiving a test data sequence at its input. The clock and data…
Methods and Systems for Recovering Intermittent Timing-Reference Signals
Granted: October 31, 2013
Application Number:
20130290766
A source-synchronous communication system in which a first integrated circuit (IC) conveys a data signal and concomitant strobe signal to a second IC. One or both ICs support hysteresis for the strobe channel that allows the second IC to distinguish between strobe preambles and noise, and thus prevent the false triggering of data capture. Hysteresis may also be employed to quickly settle the strobe channel to an inactive level after receipt of a strobe postamble.
SESSION MANAGEMENT FOR COMMUNICATION IN A HETEROGENEOUS NETWORK
Granted: October 31, 2013
Application Number:
20130290494
The present disclosure describes one embodiment of an operating center server for managing communication sessions between terminal devices such as mobile phones, VOIP phones, and computers for example. The OC server creates and maintains sessions for one or more terminal devices that allow communication between these disparate devices on disparate communication networks through the OC server.
STACKED MEMORY DEVICE WITH REDUNDANT RESOURCES TO CORRECT DEFECTS
Granted: October 24, 2013
Application Number:
20130279280
A memory device includes a stack of circuit layers, each circuit layer having formed thereon a memory circuit configured to store data and a redundant resources circuit configured to provide redundant circuitry to correct defective circuitry on at least one memory circuit formed on at least one layer in the stack. The redundant resources circuit includes a partial bank of redundant memory cells, wherein an aggregation of the partial bank of redundant memory cells in each of the circuit…
Multi-Modal Communication Interface
Granted: October 24, 2013
Application Number:
20130278296
An integrated circuit supports multiple communication modes using different input/output (IO) voltages. The IC includes a low-voltage communication circuit operating at a low IO voltage in a low-voltage mode, and a high-voltage communication circuit operating at a high IO voltage in a high-voltage mode. The low-voltage communication circuit includes low-voltage transistors in a critical path that exhibits sensitivity to a destructive voltage less than the high IO voltage. The low-voltage…
Wide Range Frequency Synthesizer with Quadrature Generation and Spur Cancellation
Granted: October 17, 2013
Application Number:
20130271186
A frequency synthesizer generates a wide range of frequencies from a single oscillator while achieving good noise performance. A cascaded phase-locked loop (PLL) circuit includes a first PLL circuit with an LC voltage controlled oscillator (VCO) and a second PLL circuit with a ring VCO. A feedforward path from the first PLL circuit to the second PLL circuit provides means and signal path for cancellation of phase noise, thereby reducing or eliminating spur and quantization effects. The…
MEMORY MODULE HAVING A WRITE-TIMING CALIBRATION MODE
Granted: October 3, 2013
Application Number:
20130262757
In memory module populated by memory components having a write-timing calibration mode, control information that specifies a write operation is received via an address/control signal path and write data corresponding to the write operation is received via a data signal path. Each memory component receives multiple delayed versions of a timing signal used to indicate that the write data is valid, and outputs signals corresponding to the multiple delayed versions of the timing signal to…
INTEGRATED CIRCUIT DEVICE HAVING PROGRAMMABLE INPUT CAPACITANCE
Granted: October 3, 2013
Application Number:
20130258755
An embodiment is directed to an integrated circuit device having programmable input capacitance. For example, a programmable register of a memory device may store a value representative of an adjustment to the input capacitance value of a control pin. An embodiment is directed to controlling the skew of a synchronous memory system by allowing programmability of the lighter loaded pins in order to increase their load to match the more heavily loaded pins. By matching lighter loaded pins…
CLOCK GENERATION FOR TIMING COMMUNICATIONS WITH RANKS OF MEMORY DEVICES
Granted: September 26, 2013
Application Number:
20130254585
A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with…
MEMORY REFRESH METHOD AND DEVICES
Granted: September 26, 2013
Application Number:
20130254475
The present disclosure describes DRAM architectures and refresh controllers that allow for scheduling of an opportunistic refresh of a DRAM device concurrently with normal row activate command directed toward the DRAM device. Each activate command affords an “opportunity” to refresh another independent row (i.e., a wordline) within a memory device with no scheduling conflict.
LOW JITTER CLOCK RECOVERY CIRCUIT
Granted: September 26, 2013
Application Number:
20130251084
A clock recovery circuit includes a first phase detector for measuring the phase difference between a first clock signal from a voltage controlled oscillator (VCO) and a data signal. A phase shifter responsive to a control signal based on this phase difference adjusts the phase of an incoming clock signal to yield a second clock signal. The phase difference between the first clock signal and the second clock signal is measured and the resulting signal is low-pass filtered to derive a…
MEMORY MODULE
Granted: September 26, 2013
Application Number:
20130250706
A memory module having memory components, a termination structure, an address/control signal path, a clock signal path, multiple data signal paths and multiple strobe signal paths. The strobe signal paths and data signal paths are coupled to respective memory components, and the address/control signal path and clock signal path are coupled in common to all the memory components. The address/control signal path extends along the memory components to the termination structure such that…
System and Method for Writing Data to an RRAM Cell
Granted: September 26, 2013
Application Number:
20130250657
A resistive RAM device includes a bit line, a word line, an RRAM cell coupled to the word line and to the bit line, a write driver and a disable circuit. The write driver is coupled to the bit line. The disable circuit stops a write operation performed by the write driver on a respective RRAM cell when a predefined condition on the bit line is achieved. The predefined condition depends on a mode of operation of the RRAM cell.
METHOD AND APPARATUS FOR SOURCE-SYNCHRONOUS SIGNALING
Granted: September 26, 2013
Application Number:
20130249612
A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce…
CONFIGURABLE PIPELINE BASED ON ERROR DETECTION MODE IN A DATA PROCESSING SYSTEM
Granted: September 19, 2013
Application Number:
20130246750
A method includes providing a data processor having an instruction pipeline, where the instruction pipeline has a plurality of instruction pipeline stages, and where the plurality of instruction pipeline stages includes a first instruction pipeline stage and a second instruction pipeline stage. The method further includes providing a data processor instruction that causes the data processor to perform a first set of computational operations during execution of the data processor…
INTEGRATED CIRCUIT DEVICE HAVING AN INJECTION-LOCKED OSCILLATOR
Granted: September 19, 2013
Application Number:
20130241662
A variable injection-strength injection-locked oscillator (ILO) is described. The variable injection-strength ILO can output an output clock signal based on an input clock signal. The variable injection-strength ILO can pause, restart, slow down, or speed up the output clock signal synchronously with respect to the input clock signal in response to receiving power mode information. Specifically, the variable injection-strength ILO can be operated under relatively strong injection when…
RECEIVER WITH TIME-VARYING THRESHOLD VOLTAGE
Granted: September 19, 2013
Application Number:
20130241622
A system for communicating information between circuits is described. A transmit circuit provides pulse-amplitude-modulation (PAM) signals via a communication channel to a receiver. A circuit in the receiver determines digital values from the received signals using a time-varying threshold voltage, which varies during the bit-time. This approach may compensate for inter-symbol interference (ISI) to increase the voltage and timing margins of the system.
DIRECT RELATIVE MEASUREMENT OF MEMORY DURABILITY
Granted: September 12, 2013
Application Number:
20130235649
Disclosed is a memory including a plurality of resistive change memory cells, including at least a first group and a second group of the memory cells and a comparison circuit configured to conduct a direct relative comparison of a remaining endurance of the first group of memory cells to a remaining endurance of the second group of memory cells.
MECHANISM FOR ENABLING FULL DATA BUS UTILIZATION WITHOUT INCREASING DATA GRANULARITY
Granted: September 12, 2013
Application Number:
20130238848
A memory is disclosed comprising a first memory portion, a second memory portion, and an interface, wherein the memory portions are electrically isolated from each other and the interface is capable of receiving a row command and a column command in the time it takes to cycle the memory once. By interleaving access requests (comprising row commands and column commands) to the different portions of the memory, and by properly timing these access requests, it is possible to achieve full…
