FIELD SEQUENTIAL COLOR ENCODING FOR DISPLAYS
Granted: September 12, 2013
Application Number:
20130235273
The optical performance is enhanced of display systems that use field sequential color and pulse width modulation to generate color and color gray scale values. Such enhancement may be achieved by various data encoding methods disclosed herein that may include temporal redistribution of bit values to mitigate color motional artifacts associated with field sequential color-based display systems, selective combination of intensity modulation, pulse width modulation, and/or the…
COMMUNICATION CHANNEL CALIBRATION FOR DRIFT CONDITIONS
Granted: September 5, 2013
Application Number:
20130230122
A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received…
MEMORY ACCESS DURING MEMORY CALIBRATION
Granted: August 29, 2013
Application Number:
20130227183
A multi-rank memory system in which calibration operations are performed between a memory controller and one rank of memory while data is transferred between the controller and other ranks of memory. A memory controller performs a calibration operation that calibrates parameters pertaining to transmission of data via a first data bus between the memory controller and a memory device in a first rank of memory. While the controller performs the calibration operation, the controller also…
RESISTANCE CHANGE MEMORY CELL CIRCUITS AND METHODS
Granted: August 22, 2013
Application Number:
20130215669
The gate of the access transistor of a 1 transistor 1 resistor (1T1R) type RRAM cell is biased relative to the source of the access transistor using a current mirror. Under the influence of a voltage applied across the 1T1R cell (e.g., via the bit line), the RRAM memory element switches from a higher resistance to a lower resistance. As the RRAM memory element switches from the higher resistance to the lower resistance, the current through the RRAM cell switches from being substantially…
DISPLAY APPARATUS WITH LIGHT GUIDE BASED SOLAR CONCENTRATOR
Granted: August 22, 2013
Application Number:
20130215122
A display apparatus includes a display, a primary light concentrator, a concentrator light guide, and a solar cell. The primary light concentrator is arranged in tandem with the display, and the primary light concentrator is configured to concentrate incident light into an array of output regions. The concentrator light guide receives light from the primary light concentrator. The concentrator light guide includes light redirecting elements aligned with the output regions of the primary…
Techniques for Storing Data and Tags in Different Memory Arrays
Granted: August 15, 2013
Application Number:
20130212331
A memory controller includes logic circuitry to generate a first data address identifying a location in a first external memory array for storing first data, a first tag address identifying a location in a second external memory array for storing a first tag, a second data address identifying a location in the second external memory array for storing second data, and a second tag address identifying a location in the first external memory array for storing a second tag. The memory…
MEMORY COMPONENTS AND CONTROLLERS THAT UTILIZE MULTIPHASE SYNCHRONOUS TIMING REFERENCES
Granted: August 15, 2013
Application Number:
20130208818
Multiple timing reference signals (e.g., clock signals) each cycling at the same frequency are distributed in a fly-by topology to a plurality of memory devices in various embodiments are presented. These multiple clock signals each have a different phase relationship to each other (e.g., quadrature). A first circuit receives a first of these clocks as a first timing reference signal. A second circuit receives a second of these clocks as a second timing reference signal. A plurality of…
REFERENCE VOLTAGE GENERATION IN A SINGLE-ENDED RECEIVER
Granted: August 8, 2013
Application Number:
20130202061
As single-ended signaling is implemented in higher-speed communications, accurate and consistent reading of the data signal becomes increasingly challenging. In particular, single-ended links can be limited by insufficient timing margins for sampling a received input signal. A single ended receiver provides for improved timing margins by adjusting a reference voltage used to sample the input signal. A calibration pattern is provided to the receiver as the input signal, and the reference…
MEMORY DEVICE COMPRISING PROGRAMMABLE COMMAND-AND-ADDRESS AND/OR DATA INTERFACES
Granted: August 1, 2013
Application Number:
20130194854
A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an…
Early Read After Write Operation Memory Device, System And Method
Granted: August 1, 2013
Application Number:
20130194879
A memory device, system and method for allowing an early read operation after one or more write operations is provided according to an embodiment of the present invention. The memory device comprises an interface for providing a first write address, a first write data, and a read address. A memory core is coupled to the interface and includes a first memory section having a first data path and a first address path and a second memory section having a second data path and a second address…
LIGHTING ASSEMBLY WITH CORNUATE LIGHT GUIDE
Granted: August 1, 2013
Application Number:
20130194809
A lighting assembly that includes a cornuate light guide and an annular light extracting and redirecting member. The light guide has a radial light input surface, an axial light input region, radial light output region and a flared region between input region and output region. Light input at the light input surface propagates to and within the light output region by total internal reflection at major surfaces of the light guide. The light extracting and redirecting member has a light…
INTEGRATED CIRCUIT WITH ADAPTIVE POWER STATE MANAGEMENT
Granted: July 25, 2013
Application Number:
20130188436
Methods and apparatuses that relate to an integrated circuit (IC) with adaptive power state management are described. The IC can be coupled with, and can control the operation of, a memory device. The IC and the memory device can be operated in multiple operational states, wherein each operational state may represent a tradeoff point between performance and power consumption. The IC may be capable of: (1) changing the operational state of the IC and/or the operational state of the memory…
LIGHTING ASSEMBLY WITH STATIC AUTOSTEREOSCOPIC IMAGE OUTPUT
Granted: July 18, 2013
Application Number:
20130182457
A lighting assembly includes a light guide in which light propagates by total internal reflection between opposed major surfaces. The light guide receives light generated by two light sources at opposed light input edges of the light guide. The light guide includes light extracting elements that respectively extract light to form a left eye image at a first region and a right eye image at a second region. The left eye and right eye images, when viewed by a viewer, form a static…
MEMORY CONTROLLER HAVING A WRITE-TIMING CALIBRATION MODE
Granted: July 11, 2013
Application Number:
20130176800
A memory controller outputs address bits and a first timing signal to a DRAM, each address bit being associated with an edge of the first timing signal and the first timing signal requiring a first propagation delay time to propagate to the DRAM. The memory controller further outputs write data bits and a second timing signal to the DRAM in association with the address bits, each of the write data bits being associated with an edge of the second timing signal and the second timing signal…
STACKED MEMORY WITH REDUNDANCY
Granted: July 11, 2013
Application Number:
20130176763
A stacked memory is disclosed including a first integrated circuit memory chip having first storage locations and stacked with a second integrated circuit memory chip. A redundant memory is shared by the first and second integrated circuit memory chips and has redundant storage locations that selectively replace corresponding storage locations in the first or second integrated circuit memory chips. The stacked memory also includes a pin interface for coupling to an external integrated…
Memory Systems and Methods for Dividing Physical Memory Locations Into Temporal Memory Locations
Granted: July 4, 2013
Application Number:
20130173871
Described are memory modules that support dynamic point-to-point extensibility using fixed-width memory die. The memory modules include data-width translators that allow the modules to vary the effective width of their external memory interfaces without varying the width of the internal memory interfaces extending between the translators and associated fixed-width dies. The data-width translators use a data-mask signal to selectively prevent memory accesses to subsets of physical…
Methods and Systems for Repairing Interior Device Layers in Three-Dimensional Integrated Circuits
Granted: July 4, 2013
Application Number:
20130168674
A three-dimensional integrated circuit (3D-IC) includes a stack of semiconductor wafers, each of which includes a substrate and a device layer. Programmable components, such as memory arrays or logic circuits, are formed within the device layers. Some of the programmable components are redundant, and can be substituted for defective components by programming passive memory elements in a separate conductive layer provided for this purpose. The separate conductive layer is devoid of active…
HIGH-ACCURACY DETECTION IN COLLABORATIVE TRACKING SYSTEMS
Granted: June 27, 2013
Application Number:
20130162460
An electronic device for wirelessly tracking the position of a second electronic device is disclosed. The electronic device includes transceiver circuitry and processing circuitry. The transceiver circuitry includes a beacon generator to generate a beacon at a particular frequency and direction. An antenna array transmits the beacon, and receives at least one modulated reflected beacon from the second electronic device. The transceiver circuitry also includes a discriminator to…
MEMORY CONTROLLER WITH FAST REACQUISITION OF READ TIMING TO SUPPORT RANK SWITCHING
Granted: June 20, 2013
Application Number:
20130159657
Techniques for performing fast timing reacquisition of read timing in a memory controller to support rank switching device are described. During operation, a memory controller receives read data for a read operation, wherein the read data includes a calibration preamble. The memory controller uses the calibration preamble to perform a fast timing reacquisition operation to compensate for a timing drift between a clock path and a data path for the read data. In particular, the memory…
THERMAL ANNEAL USING WORD-LINE HEATING ELEMENT
Granted: June 13, 2013
Application Number:
20130148437
In response to detecting an event during operation of an integrated-circuit memory device containing charge-storing memory cells, an electric current is enabled to flow through a word line coupled to the charge-storing memory cells for a brief interval to heat the charge-storing memory cells to an annealing temperature range.
