POWER-MANAGEMENT FOR INTEGRATED CIRCUITS
Granted: December 19, 2013
Application Number:
20130339775
An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.
CROSS-THREADED MEMORY SYSTEM
Granted: December 19, 2013
Application Number:
20130339631
In a data processing system, a buffer integrated-circuit (IC) device includes multiple control interfaces, multiple memory interfaces and switching circuitry to couple each of the control interfaces concurrently to a respective one of the memory interfaces in accordance with a path selection value. A plurality of requestor IC devices are coupled respectively to the control interfaces, and a plurality of memory IC devices are coupled respectively to the memory interfaces.
CONTACT AND IDENTITY MANAGEMENT IN A HETEROGENEOUS NETWORK WITH DISPARATE CLIENTS
Granted: December 19, 2013
Application Number:
20130339464
The present disclosure describes one embodiment of an operating center server for managing contact information and user identifiers of users who communicate with others using a plurality of different communication platforms that operate on disparate networks (e.g., a cellular network or a wireless local area network). The operating center server converges cellular connectivity services (e.g., cellular calls or SMS messages) with internet protocol (IP) services (e.g., email or VOIP calls)…
ITERATIVE INTERFERENCE SUPPRESSION USING MIXED FEEDBACK WEIGHTS AND STABILIZING STEP SIZES
Granted: December 19, 2013
Application Number:
20130336363
A receiver is configured for canceling intra-cell and inter-cell interference in coded, multiple-access, spread-spectrum transmissions that propagate through frequency-selective communication channels. The receiver employs iterative symbol-estimate weighting, subtractive cancellation with a stabilizing step-size, and mixed-decision symbol estimate. Receiver embodiments may be implemented explicitly in software of programmed hardware, or implicitly in standard Rake-based hardware either…
TIMING-DRIFT CALIBRATION
Granted: December 19, 2013
Application Number:
20130336080
The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the…
MEMORY BANDWIDTH AGGREGATION USING SIMULTANEOUS ACCESS OF STACKED SEMICONDUCTOR MEMORY DIE
Granted: December 19, 2013
Application Number:
20130336039
A packaged semiconductor device includes a data pin, a first memory die, and a second memory die stacked with the first memory die. The first memory die includes a first data interface coupled to the data pin and a first memory core having a plurality of banks. The second memory die includes a second memory core having a plurality of banks. A respective bank of the first memory core and a respective bank of the second memory core perform parallel row access operations in response to a…
METHODS AND APPARATUSES FOR ADDRESSING MEMORY CACHES
Granted: December 12, 2013
Application Number:
20130332668
A cache memory includes cache lines to store information. The stored information is associated with physical addresses that include first, second, and third distinct portions. The cache lines are indexed by the second portions of respective physical addresses associated with the stored information. The cache memory also includes one or more tables, each of which includes respective table entries that are indexed by the first portions of the respective physical addresses. The respective…
LIGHT REDIRECTING FILMS AND FILM SYSTEMS
Granted: December 12, 2013
Application Number:
20130329432
An optical assembly comprises a light emitting panel having a light output surface and a light redirecting film located to receive light emitted from the light output surface. The light output surface has a non-uniform directional light output distribution. The light redirecting film has a pattern of individual optical elements of well defined shape that vary at different locations on the light redirecting film to redistribute the light received from the light output surface within a…
HIGH-SPEED SIGNALING SYSTEMS WITH ADAPTABLE PRE-EMPHASIS AND EQUALIZATION
Granted: December 5, 2013
Application Number:
20130322506
A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without…
SIGNAL LINE ROUTING TO REDUCE CROSSTALK EFFECTS
Granted: December 5, 2013
Application Number:
20130322510
A signaling system is disclosed. The system includes a transmitter comprising an encoder to encode a data signal such that the encoded data signal has a balanced number of logical 1s and 0s. The system also includes a receiver having a decoder to decode the encoded data signal, and a link. The link is coupled between the transmitter and the receiver to route the encoded data signal. The link comprises three or more conductive lines that are routed along a path in parallel between the…
OPTICALLY TRANSMISSIVE SUBSTRATES AND LIGHT EMITTING ASSEMBLIES AND METHODS OF MAKING SAME, AND METHODS OF DISPLAYING IMAGES USING THE OPTICALLY TRANSMISSIVE SUBSTRATES AND LIGHT EMITTING ASSEMBLIES
Granted: December 5, 2013
Application Number:
20130322120
Images are displayed in response to a video signal using a light emitting assembly having one or more optically transmissive substrates, films or sheets, each having at least one pattern of optical elements on or in the substrates, films or sheets. A plurality of light sources are configured to illuminate one or more output areas of one or more of the substrates, films or sheets. The light emitting assembly is configured to emit light through the pattern of optical elements and produce a…
METHODS AND APPARATUS FOR TESTING INACCESSIBLE INTERFACE CIRCUITS IN A SEMICONDUCTOR DEVICE
Granted: December 5, 2013
Application Number:
20130321022
A semiconductor IC device comprises a timing circuit to transfer a timing signal, the timing circuit being configured to receive a first test signal and to effect a delay in the timing signal in response to the first test signal, the first test signal including a first timing event. The semiconductor IC device further comprises an interface circuit configured to transfer the data signal in response to the timing signal, the interface circuit being further configured to receive a second…
DISTRIBUTED ON-CHIP DECOUPLING APPARATUS AND METHOD USING PACKAGE INTERCONNECT
Granted: December 5, 2013
Application Number:
20130320560
An integrated circuit device is disclosed. The integrated circuit device includes a semiconductor die fabricated by a front-end semiconductor process and having oppositely disposed planar surfaces. The semiconductor die is formed with semiconductor devices, power supply circuitry coupled to the semiconductor devices, decoupling capacitance circuitry, and through-vias. The through-vias include a first group of vias coupled to the power supply circuitry and a second group of vias coupled…
METHODS AND CIRCUITS FOR ADAPTIVE EQUALIZATION
Granted: November 28, 2013
Application Number:
20130315290
An integrated circuit equalizes a data signal expressed as a series of symbols. The symbols form data patterns with different frequency components. By considering these patterns, the integrated circuit can experiment with equalization settings specific to a subset of the frequency components, thereby finding an equalization control setting that optimizes equalization. Optimization can be accomplished by setting the equalizer to maximize symbol amplitude.
LIGHT EMITTING PANEL ASSEMBLIES
Granted: November 28, 2013
Application Number:
20130314944
An optical assembly comprises light sources and a light emitting panel member having an input edge to which each of the light sources is optically coupled at a different location along the input edge. Different sets of individual optical deformities on or in at least one of the sides of the panel member each have at least one surface that is shaped or oriented to extract light propagating in the same direction through the panel member in different directions for viewing from different…
DELAY FAULT TESTING FOR CHIP I/O
Granted: November 28, 2013
Application Number:
20130314102
An integrated circuit (IC) chip is provided. The IC chip includes a signal output via which an outgoing signal is transmitted, and a signal input via which an incoming data signal is received. Also included on the IC ship is a pass circuit to couple the signal output to the signal input during testing of the IC chip. Furthermore, a delay circuit produces a first timing signal and a second timing signal during testing of the IC chip. The second timing signal is delayed from the first…
HYBRID VOLATILE AND NON-VOLATILE MEMORY DEVICE
Granted: November 21, 2013
Application Number:
20130308383
A composite, hybrid memory device including a first storage die having an array of volatile storage cells and a second storage die having an array of non-volatile storage cells disposed within an integrated circuit package. The hybrid memory device includes a shared interface circuit to receive memory access commands directed to the first storage die and the second storage die and to convey read and write data between an external data path and the first and second storage dice.
SIMULTANEOUS SWITCHING NOISE CANCELLATION BY ADJUSTING REFERENCE VOLTAGE AND SAMPLING CLOCK PHASE
Granted: November 21, 2013
Application Number:
20130307607
A data signal is transmitted from a first circuit to a second circuit, with noise and/or jitter added to the data signal by supply noise in the power distribution network in the first circuit and/or a second circuit being effectively canceled out by adjustment of the reference voltage and/or the phase of the sampling clock used for sampling of the data signal in a manner that effectively mimics such noise and/or jitter added to the data signal. The second circuit uses a filter that has…
MULTI-VALUED ON-DIE TERMINATION
Granted: November 21, 2013
Application Number:
20130307584
An integrated circuit memory device stores a plurality of digital values that specify respective termination impedances. The memory device switchably couples respective sets of load elements to a data input/output (I/O) to apply the termination impedances specified by the digital values, including, applying a first termination impedance to the data I/O during an idle state of the memory device, applying a first one of two non-equal termination impedances to the data I/O while the memory…
Supporting Calibration For Sub-Rate Operation In Clocked Memory Systems
Granted: November 14, 2013
Application Number:
20130301368
The disclosed embodiments related to a clocked memory system which performs a calibration operation at a full-rate frequency to determine a full-rate calibration state that specifies a delay between a clock signal and a corresponding data signal in the clocked memory system. Next, the clocked memory system uses the full-rate calibration state to calculate a sub-rate calibration state, which is associated with a sub-rate frequency (e.g., ½, ¼ or ? of the full-rate frequency). The system…
