MEMORY CONTROLLER WITH RECONFIGURABLE HARDWARE
Granted: May 30, 2013
Application Number:
20130138911
Memory controller concepts are disclosed in which hardware resources of a memory controller can be re-used or re-configured to accommodate various different memory configurations. The memory configuration may be stored in mode register bits (228), settable by a host or operating system. By re-configuring or reallocating certain resources of a memory controller, for example command logic blocks (A,B,C,D in FIG. 1A), a single controller design can be used to interface efficiently with a…
MEMORY CONTROLLER AND METHOD FOR TUNED ADDRESS MAPPING
Granted: May 23, 2013
Application Number:
20130132704
A memory system maps physical addresses to device addresses in a way that reduces power consumption. The system includes circuitry for deriving efficiency measures for memory usage and selects from among various address-mapping schemes to improve efficiency. The address-mapping schemes can be tailored for a given memory configuration or a specific mixture of active applications or application threads. Schemes tailored for a given mixture of applications or application threads can be…
MEMORY CONTROLLER AND MEMORY DEVICE COMMAND PROTOCOL
Granted: May 23, 2013
Application Number:
20130132685
Embodiments generally relate to a command protocol and/or related circuits and apparatus for communication between a memory device and a memory controller. In one embodiment, the memory controller includes an interface for transmitting commands to the memory device, wherein the memory device includes bitline multiplexers, and accessing of memory cells within the memory device is carried out by a command protocol sequence that includes a wordline selection, followed by bitline selections…
INTEGRATED CIRCUIT COMPRISING A DELAY-LOCKED LOOP
Granted: May 16, 2013
Application Number:
20130121094
Embodiments of an integrated circuit (IC) comprising a delay-locked loop (DLL) are described. Some embodiments include first circuitry to generate a first clock signal by delaying an input clock signal by a first delay, second circuitry to determine a code based on the input clock signal and the first clock signal, and third circuitry to produce an output clock signal based on the input clock signal and the code. In some embodiments, the power consumption of the DLL circuitry is reduced…
MULTI-MODAL MEMORY INTERFACE
Granted: May 9, 2013
Application Number:
20130114363
A multi-modal memory interface that supports each of current-mode and voltage-mode signaling by a memory controller with a memory which includes one or more memory devices. In a first type of system, the memory interface is configured to provide differential current-mode signaling from the memory controller to a first type of memory, and differential voltage-mode signaling from the memory to the memory controller. In contrast, in a second type of system, the memory interface is…
MEMORY METHODS AND SYSTEMS WITH ADIABATIC SWITCHING
Granted: May 9, 2013
Application Number:
20130114353
A memory system includes wordlines and pairs of complementary bitlines that provide access to memory storage elements. Capacitive and resistive loads associated with wordlines and bitlines are driven relatively slowly between voltage levels to reduce peak current, and thus power dissipation. Power dissipation is further reduced by charging complementary bitlines at substantially different rates.
LIGHT REDIRECTING FILMS AND FILM SYSTEMS
Granted: May 2, 2013
Application Number:
20130107543
Light redirecting film comprises a thin optically transparent substrate having a pattern of individual optical elements formed as projections on a light exit surface of the film. At least some of the projections comprise a dome-shaped surface on the light exit surface.
DRIFT DETECTION IN TIMING SIGNAL FORWARDED FROM MEMORY CONTROLLER TO MEMORY DEVICE
Granted: May 2, 2013
Application Number:
20130111256
A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device…
MEMORY CONTROLLER WITH STAGGERED REQUEST SIGNAL OUTPUT
Granted: May 2, 2013
Application Number:
20130111176
A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.
Cache Memory That Supports Tagless Addressing
Granted: May 2, 2013
Application Number:
20130111132
Embodiments related to a cache memory that supports tagless addressing are disclosed. Some embodiments receive a request to perform a memory access, wherein the request includes a virtual address. In response, the system performs an address-translation operation, which translates the virtual address into both a physical address and a cache address. Next, the system uses the physical address to access one or more levels of physically addressed cache memory, wherein accessing a given level…
Methods and Systems for Near-Field MIMO Communications
Granted: April 25, 2013
Application Number:
20130101005
A near-field communication (NFC) system supports increased data rates using a multiple-input-multiple-output (MIMO) interface. Multiple receive antennas are positioned within the near field of multiple transmit antennas. The NFC system uses a combination of antenna spacing and polarizations to reduce correlation between channels, and thus improves performance by creating closer to ideal MIMO operation. Such system can also be operated as parallel SISO links with reduced cross-channel…
INTERNAL COLLECTING REFLECTOR OPTICS FOR LEDS
Granted: April 25, 2013
Application Number:
20130100664
An optical system is disclosed that uses an LED light source. The light output is coupled to an optic element formed from a material with a high refractive index. The coupling of the light to the high index material significantly reduces the cone angle of the light. The system is very efficient in that nearly all the light generated by the LED is directed to the intended subject.
Address Mapping in Memory Systems
Granted: April 18, 2013
Application Number:
20130097403
A memory system includes an address mapping circuit. The address mapping circuit receives an input memory address having a first set of address bits. The address mapping circuit applies a logic function to the input memory address to generate a mapped memory address. The logic function uses at least a subset of the first set of address bits in two separate operations that respectively determine two portions of the mapped memory address.
METHODS AND APPARATUS FOR SYNCHRONIZING COMMUNICATION WITH A MEMORY CONTROLLER
Granted: April 18, 2013
Application Number:
20130094310
A memory controller receives data and phase-providing signals from a memory device. The phase-providing signal is not a clock signal, but is used by the memory controller to phase align a local data-sampling signal with the incoming data. The memory controller samples the data signal with the data-sampling signal. The memory controller can perform maintenance operations to update the phase relationship between the phase-providing and data-sampling signals.
Integrated Circuit Having Receiver Jitter Tolerance ("JTOL") Measurement
Granted: April 18, 2013
Application Number:
20130093433
An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.
Sharing a Check Bit Memory Device Between Groups of Memory Devices
Granted: April 4, 2013
Application Number:
20130086449
A memory system that supports error detection and correction (EDC) coverage. The memory system includes a memory module with at least two groups of memory devices that store data and another memory device that stores error checking information (e.g., Error Correcting Code) for both groups of memory devices. The memory module also includes a memory buffer that determines an address for accessing the error checking information based on whether data is transferred with the first group of…
ENHANCING MOBILE DEVICE COVERAGE
Granted: March 21, 2013
Application Number:
20130072171
Embodiments of methods, apparatuses and systems for operating a mobile device are disclosed. One method includes receiving at the mobile device, a call initiated by an endpoint device. Upon determining that an identifier of the call is not associated with at least one preferred operating center, the call is redirected to the at least one preferred operating center. After the redirecting, the redirected call is received by the mobile device from the at least one preferred operating…
Memory Systems and Methods for Dynamically Phase Adjusting A Write Strobe and Data to Account for Receive-Clock Drift
Granted: March 14, 2013
Application Number:
20130064023
A memory system includes a memory controller that writes data to and reads data from a memory device. A write data strobe accompanying the write data indicates to the memory device when the write data is valid, whereas a read strobe accompanying data from the memory device indicates to the memory controller when the read data is valid. The memory controller adaptively controls the phase of the write data strobe to compensate for timing drift at the memory device. The memory controller…
Methods and Circuits for Duty-Cycle Correction
Granted: March 14, 2013
Application Number:
20130063191
A duty-cycle correction circuit calibrates the duty cycle of a periodic input signal. The correction circuit includes a state machine that samples the input signal using a sample signal of a sample period. The sample period is selected to scan a period of the input signal over a number of sample periods. The resultant difference between the number of high and low samples provides a measure of the duty cycle deviation from e.g. 50%. An adjustable delay circuit adjusts the relative timing…
CODED DIFFERENTIAL INTERSYMBOL INTERFERENCE REDUCTION
Granted: February 28, 2013
Application Number:
20130051162
Encoder and decoder circuits that encode and decode a series of data words to/from a series of code words. The data words include L symbols. The code words include M symbols, where M is larger than L. A set of tightly coupled M links to convey respective symbols in each of the series of code words. The code words are selected such that between every two consecutive code words in a series of code words, an equal number of transitions from low to high and high to low occur on a subset of…
