STROBE-OFFSET CONTROL CIRCUIT
Granted: February 21, 2013
Application Number:
20130044552
A method of operation in a memory controller is disclosed. The method includes receiving a strobe signal having a first phase relationship with respect to first data propagating on a first data line, and a second phase relationship with respect to second data propagating on a second data line. A first sample signal is generated based on the first phase relationship and a second sample signal is generated based on the second phase relationship. The first data signal is received using a…
Locked Loop Circuit With Clock Hold Function
Granted: February 14, 2013
Application Number:
20130039396
A locked loop circuit having a clock hold function. The locked loop circuit includes a select circuit, phase mixing circuit, hold signal generator and latch circuit. The select circuit selects one of a plurality of phase values in response to a select signal, and the phase mixing circuit generates a first clock signal having a phase angle according to the selected phase value. The hold signal generator asserts a hold signal in response to a transition of the select signal, and the latch…
LIGHT BULB WITH THERMAL FEATURES
Granted: February 14, 2013
Application Number:
20130038195
A light bulb includes a light guide, light source, and housing. The light guide is configured as an open-ended hollow body surrounding an internal volume and defining a longitudinal axis. The light guide has inner and outer major surfaces. The light source is configured to edge light the light guide. The housing is at one end of the light guide. In one embodiment, fins extend from the housing adjacent the outer major surface, each fin separated from the outer major surface by an air gap…
Memory Signal Buffers and Modules Supporting Variable Access Granularity
Granted: February 7, 2013
Application Number:
20130036273
Described are memory modules that include a configurable signal buffer that manages communication between memory devices and a memory controller. The buffer can be configured to support threading to reduce access granularity, the frequency of row-activation, or both. The buffer can translate controller commands to access information of a specified granularity into subcommands seeking to access information of reduced granularity. The reduced-granularity information can then be combined,…
Adjusting Clock Error Across A Circuit Interface
Granted: February 7, 2013
Application Number:
20130034134
A system is provided with clock skew measurement and correction technology. A first circuit or memory controller 4 includes measuring circuits to measure relative timing or phase offsets of multiple clock signals of a second circuit or memory 6. One measuring circuit is configured for incremental changing of the phase of a transmitted test data sequence to measure and correct timing of a memory receiver circuit's quadrature clocks based on results of a data comparison of transmitted and…
Memory Buffers and Modules Supporting Dynamic Point-to-Point Connections
Granted: February 7, 2013
Application Number:
20130033954
A memory module comprises a module interface having module data-group ports to communicate data as respective data groups, a command port to receive memory-access commands, a first memory device including a first device data-group port, a second memory device including a second device data-group port, and a signal buffer coupled between the module interface and each of the first and second devices. In a first mode, in response to the memory-access commands, the signal buffer communicates…
FREQUENCY-AGILE STROBE WINDOW GENERATION
Granted: February 7, 2013
Application Number:
20130033946
The disclosed embodiments relate to components of a memory system that support frequency-agile strobe enable window generation during read accesses. In specific embodiments, this memory system contains a memory controller which includes a timing circuit to synchronize a timing-enable signal with a timing signal returned from a read path, wherein the timing signal includes a delay from the read path. In some embodiments, the timing circuit further comprises two calibration loops. The…
LIGHTING ASSEMBLY WITH CONFIGURABLE ILLUMINATION PROFILE
Granted: February 7, 2013
Application Number:
20130033900
A lighting assembly includes an edge-lit light guide and a light redirecting member. Light extracting elements at the light guide extract light from the light guide as intermediate light. Light redirecting elements at the light redirecting film are configured to redirect the intermediate light received from the light guide to illuminate a target surface in accordance with a defined illumination profile.
Techniques for Interconnecting Stacked Dies Using Connection Sites
Granted: February 7, 2013
Application Number:
20130032950
An integrated circuit die includes conductive connection sites located at least on a surface of the integrated circuit die within a contiguous region thereof. The integrated circuit also includes a core circuit located outside the contiguous region. The core circuit is coupled to at least one of the connection sites.
Calibration Methods and Circuits to Calibrate Drive Current and Termination Impedance
Granted: January 24, 2013
Application Number:
20130021056
Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination…
LIGHTING ASSEMBLY WITH CONTROLLED CONFIGURABLE LIGHT REDIRECTION
Granted: January 17, 2013
Application Number:
20130016526
A lighting assembly has an edge-lit light guide having a light output surface through which light is extracted by light extracting optical elements. The extracted light has a maximum intensity at low light ray angles relative to the light output surface. A light redirecting member has an arrangement of light redirecting optical elements configured to redirect the extracted light incident thereon to provide a pattern of redirected light. A light focusing member has light focusing optical…
Levelization of Memory Interface for Communicating with Multiple Memory Devices
Granted: January 10, 2013
Application Number:
20130013878
In a memory system in which a system clock signal is forwarded from the memory controller to multiple memory devices, the phase of the system clock signal forwarded to the slower memory device is advanced relative to the system clock signal forwarded to the faster memory device by a phase corresponding to the skew on the data links corresponding to the memory devices. This causes the state machine of the slower memory device to change states and advance earlier than the state machine in…
Methods and Apparatus for Transmission of Data
Granted: January 10, 2013
Application Number:
20130009686
A system includes a transmitter circuit and a receiver circuit that are coupled together through transmission lines. The transmitter circuit generates an early timing signal, a nominal timing signal, and a late timing signal. A multiplexer circuit selects between the early and the late timing signals based on a data signal to generate an encoded output signal that encodes the data signal. The nominal timing signal and the encoded output signal are transmitted through the transmission…
Adaptive Equalization Using Correlation Of Edge Samples With Data Patterns
Granted: December 27, 2012
Application Number:
20120327993
An integrated receiver supports adaptive receive equalization. An incoming bit stream is sampled using edge and data clock signals derived from a reference clock signal. A phase detector determines whether the edge and data clock signals are in phase with the incoming data, while some clock recovery circuitry adjusts the edge and data clock signals as required to match their phases to the incoming data. The receiver employs the edge and data samples used to recover the edge and data…
Methods and Circuits for Dynamically Scaling DRAM Power and Performance
Granted: December 27, 2012
Application Number:
20120327726
A memory system supports high-performance and low-power modes. The memory system includes a memory core and a core interface. The memory core employs core supply voltages that remain the same in both modes. Supply voltages and signaling rates for the core interface may be scaled down to save power. Level shifters between the memory core and core interface level shift signals as needed to accommodate the signaling voltages used by the core interface in the different modes.
Decision Feedback Equalizer
Granted: December 13, 2012
Application Number:
20120314756
A decision-feedback equalizer (DFE) samples an analog input signal against M references during the same symbol time to produce M speculative samples. Select logic in the DFE then decodes N bits resolved previously for previous symbol times to select one of the M speculative samples as the present resolved bit. The present resolved bit is then stored as the most recent previously resolved bit in preparation for the next symbol time. The select logic can be can be programmable to…
Memory Architecture With Redundant Resources
Granted: December 13, 2012
Application Number:
20120314520
A hierarchical memory architecture includes an array of memory sub-arrays, each of which includes an array of memory cells. Each sub-array is supported by local wordlines, local column-select lines, and bitlines. The local wordlines are controlled using main wordlines that extend past multiple sub-arrays in a direction parallel to a first axis, whereas the local column-select lines are controlled using main column-select lines that extend between sub-arrays in a direction perpendicular…
Multilevel DRAM
Granted: December 13, 2012
Application Number:
20120314484
A multi-level dynamic random-access memory (MLDRAM) represents an original bit combination of more than one bit using a cell voltage stored in a single memory cell. The cell voltage is in one of a number of discrete analog voltage ranges each corresponding to a respective one of the possible values of the bit combination. In reading a selected memory cell, stored charge is conveyed via a local bitline to a preamplifier. The preamplifier amplifies the signal on the local bitline and…
LIGHTING ASSEMBLY
Granted: December 13, 2012
Application Number:
20120314449
A lighting assembly includes a transparent light guide having first and second major surfaces and a light input edge, and is configured to propagate light by total internal reflection. A light source located adjacent the light input edge is selectively operable to edge light the light guide. First light extracting elements at the first major surface are configured to extract light through the first major surface with a first light ray angle distribution. Second light extracting elements…
REDUCING CROSSTALK BETWEEN MULTIPLE INTERCONNECTS
Granted: December 6, 2012
Application Number:
20120306568
Embodiments reduce crosstalk between multiple interconnects in a printed circuit board environment. Further, embodiments perform frequency-dependent modal decomposition of characteristics of two or more interconnects spanning one or more integrated circuits on an interconnect substrate. In addition, each interconnect includes one or more cascaded coupled traces, where the cascaded coupled traces have one or more discontinuities in a heterogeneous medium.
