ANTENNA ARRAY WITH FLEXIBLE INTERCONNECT FOR A MOBILE WIRELESS DEVICE
Granted: September 23, 2010
Application Number:
20100240327
An antenna array can be mounted on a flexible substrate and connected by a flexible interconnect to an integrated circuit such as a radio frequency front end. The antenna array can be mounted in a device housing that includes radio frequency interference (RFI) shielding. The antenna array is aligned with and next to an area of the housing that is not shielded against RFI.
RECONFIGURABLE POINT-TO-POINT MEMORY INTERFACE
Granted: September 16, 2010
Application Number:
20100235554
Embodiments of an apparatus are described. An interface circuit in this apparatus receives or transmits digital signals on a bus and is configured to alternatively operate as either a data-bus interface circuit or a control-bus interface circuit in dependence upon a mode setting stored in a register. For example, the interface circuit may be pre-configured to interpret a line of an external bus as either a data line or a control line in accordance with the stored mode setting. Moreover,…
SIMPLIFIED RECEIVER FOR USE IN MULTI-WIRE COMMUNICATION
Granted: September 16, 2010
Application Number:
20100235673
An encoder encodes data into a series of parallel codewords. Each codeword is expressed two sets of logic values (e.g., a set of logic 0s and a set of logic 1s) on output nodes. The encoder selects a current codeword from a group of codewords in a codespace which does not overlap the other group of codewords, i.e., codewords in a given group of codewords are not included in any other group of codewords in the codespace. This property allows a receiver of the codewords to be simplified.…
DELAY LOCK LOOP DELAY ADJUSTING METHOD AND APPARATUS
Granted: September 9, 2010
Application Number:
20100228514
Systems and methods for synchronizing communication between devices include using a test circuit to measure a propagation time through a delay circuit. The propagation time is used to determine an initial delay value within a delay lock loop. This delay value is then changed until a preferred delay value, resulting in synchronization, is found. In various embodiments, used of the initial delay value increases the speed, reliability or other beneficial features of the synchronization.
EDGE-BASED SAMPLER OFFSET CORRECTION
Granted: September 2, 2010
Application Number:
20100220828
Embodiments of a circuit are described. This circuit includes a receiver circuit including a first sampler (312-1) and a second” sampler (312-2). A clock-data-recovery circuit (324) in the receiver circuit adjusts a sample time of the receiver circuit so that the sample time is proximate to a signal crossing point at an edge of an eye pattern associated with received signals. An offset-calibration circuit (326) in the receiver circuit determines and adjusts an offset voltage of a given…
Variable-width memory
Granted: September 2, 2010
Application Number:
20100223426
Described is a memory system in which the memory core organization changes with device width. The number of physical memory banks accessed reduces with device width, resulting in reduced power usage for relatively narrow memory configurations. Increasing the number of logic memory banks for narrow memory widths reduces the likelihood of bank conflicts, and consequently improves speed performance.
VOLTAGE-STEPPED LOW-POWER MEMORY DEVICE
Granted: August 26, 2010
Application Number:
20100214822
This disclosure has described a system for charging a capacitive energy storage device of at least one memory cell within an integrated circuit device from an initial voltage to a final voltage, wherein the integrated circuit device includes a plurality of memory cells which are formed at least in part by capacitive energy storage devices. During operation, the system charges the capacitive energy storage device from the initial voltage to the final voltage stepwise through one or more…
Adaptive Equalization Using Correlation of Edge Samples With Data Patterns
Granted: August 26, 2010
Application Number:
20100215091
An integrated receiver supports adaptive receive equalization. An incoming bit stream is sampled using edge and data clock signals derived from a reference clock signal. A phase detector determines whether the edge and data clock signals are in phase with the incoming data, while some clock recovery circuitry adjusts the edge and data clock signals as required to match their phases to the incoming data. The receiver employs the edge and data samples used to recover the edge and data…
TECHNIQUES FOR MULTI-WIRE ENCODING WITH AN EMBEDDED CLOCK
Granted: August 26, 2010
Application Number:
20100215118
Techniques for multi-wire encoding with an embedded clock are disclosed. In one particular exemplary embodiment, the techniques may be realized as a transmitter component. The transmitter component may comprise at least one encoder module to generate a set of symbols, each symbol being represented by a combination of signal levels on a set of wires. The transmitter component may also comprise at least one signaling module to transmit one or more of the symbols over the set of wires…
Iterative Interference Cancellation Using Mixed Feedback Weights and Stabilizing Step Sizes
Granted: August 19, 2010
Application Number:
20100208774
A receiver is configured for canceling intra-cell and inter-cell interference in coded, multiple-access, spread-spectrum transmissions that propagate through frequency-selective communication channels. The receiver employs iterative symbol-estimate weighting, subtractive cancellation with a stabilizing step-size, and mixed-decision symbol estimates. Receiver embodiments may be implemented explicitly in software or programmed hardware, or implicitly in standard Rake-based hardware either…
Memory System With Point-to-Point Request Interconnect
Granted: August 19, 2010
Application Number:
20100211748
A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The…
NON-VOLATILE MEMORY DEVICE WITH REDUCED WRITE-ERASE CYCLE TIME
Granted: August 19, 2010
Application Number:
20100207189
A transistor includes a substrate having a surface, where a first region and a second region of the substrate are doped with a first type of dopant, and where a third region of the substrate between the first region and the second region is doped with a second type of dopant. An insulator layer is deposited above a portion of the surface, which includes the third region, and a gate layer is deposited above the insulator layer. An encapsulation layer encloses ends of the gate layer,…
REFERENCE VOLTAGE AND IMPEDANCE CALIBRATION IN A MULTI-MODE INTERFACE
Granted: August 12, 2010
Application Number:
20100202227
A memory controller includes a transmit circuit coupled to an output node and a receive circuit coupled to an input node. The transmit circuit transmits first data to a memory device through the output node and the receive circuit is configured to receive second data from the memory device through the input node. The memory controller includes a calibration circuit and control logic coupled to the calibration circuit, where the calibration circuit and the control logic are configured to…
COMMUNICATION USING CONTINUOUS-PHASE MODULATED SIGNALS
Granted: August 12, 2010
Application Number:
20100202565
Embodiments of a circuit are described. In this circuit, a modulation circuit provides a first modulated electrical signal and a second modulated electrical signal, where a given modulated electrical signal, which can be either the first modulated electrical signal or the second modulated electrical signal, includes minimum-shift keying (MSK) modulated data. Moreover, a first phase-adjustment element, which is coupled to the modulation circuit, sets a relative phase between the first…
Generating interface adjustment signals in a device-to-device interconnection system
Granted: August 12, 2010
Application Number:
20100205343
Described are a system and method to control interface timing and/or voltage operations of signals transmitted between devices. A processor may be coupled through one or more bus interfaces of a bus to one or more corresponding interface timing and/or voltage comparison circuits and corresponding interface timing and/or voltage adjustment circuits.
TRANSFORMING VARIABLE DOMAINS FOR LINEAR CIRCUIT ANALYSIS
Granted: August 5, 2010
Application Number:
20100199237
Embodiments in the present disclosure pertain to domain translators. A domain translator converts a variable from one domain to a different domain. Domains include, but are not limited to, voltage, current, frequency, phase, delay, and duty-cycle. In particular, domain translators enable conversion between standard voltage and current domains commonly used by circuit simulators to other domains such as frequency, phase, delay, duty-cycle, etc., so that linear analysis can be performed on…
CLOCK SYNCHRONIZATION IN A MEMORY SYSTEM
Granted: July 29, 2010
Application Number:
20100188910
A system and method for synchronizing a strobed memory system 10. During memory read and/or memory write operations the corresponding data strobe is sampled at the data destination 50/55 according to a local clock signal 71/73. Based on the results of the sampling, the data strobe and local clock signal are synchronized. In this manner, the data is synchronized to the local clock signal so that sampling of data at the data destination can be performed according to the local clock signal…
MULTI-ANTENNA TRANSMITTER FOR MULTI-TONE SIGNALING
Granted: July 22, 2010
Application Number:
20100183090
Embodiments of a communication circuit are described. This communication circuit includes an input node (212) to receive a set of data symbols and a partitioner (216) coupled to the input node. The partitioner is to divide the set of data symbols into M irregular subgroups of data symbols, a given one of which includes non-consecutive data symbols in the set of data symbols. Moreover, this given irregular subgroup of data symbols includes at least two pairs of adjacent data symbols…
IN-DRAM CYCLE-BASED LEVELIZATION
Granted: July 22, 2010
Application Number:
20100185810
Systems and methods are provided for in-DRAM cycle-based levelization. In a multi-rank, multi-lane memory system, an in-DRAM cycle-based levelization mechanism couples to a memory device in a rank and individually controls additive write latency and/or additive read latency for the memory device. The in-DRAM levelization mechanism ensures that a distribution of relative total write or read latencies across the lanes in the rank is substantially similar to that in another rank.
TECHNIQUES FOR IMPROVED TIMING CONTROL OF MEMORY DEVICES
Granted: July 15, 2010
Application Number:
20100180143
Techniques for improved timing control of memory devices are disclosed. In one embodiment, the techniques may be realized as a memory controller to communicate with a memory device via a communications link. The memory controller may comprise a memory interface to exchange data with the memory device via a set of N conductors according to at least one clock, the data being encoded such that each M bits of data are represented by at least one symbol and each symbol is associated with a…
