Clock-Data Recovery ("CDR") Circuit, Apparatus And Method For Variable Frequency Data
Granted: June 17, 2010
Application Number:
20100150290
A circuit, such as a CDR circuit, includes a sampler to receive a data signal having a variable data bit-rate responsive to a clock signal in an embodiment of the present invention. A clock circuit is coupled to the sampler and generates the clock signal responsive to a selectable update rate and a selectable phase adjust step-size. In a second embodiment of the present invention, the clock circuit includes a Stall logic that is coupled to first, second and third stages and is capable to…
MULTI-ANTENNA BEAM-FORMING SYSTEM FOR TRANSMITTING CONSTANT ENVELOPE SIGNALS DECOMPOSED FROM A VARIABLE ENVELOPE SIGNAL
Granted: June 17, 2010
Application Number:
20100149039
Embodiments in the present disclosure pertain to a multi-antenna beam-forming system for transmitting constant envelope signals decomposed from a variable envelope signal. The variable envelope signal is decomposed into two constant envelope signals. Each of the constant envelope signals are separately amplified by power amplifiers and transmitted over separate antennas. Beam steering delays can be added to the transmit paths of the constant envelope signals to direct the beam to the…
Methods and Systems for Transmitting Data by Modulating Transmitter Filter Coefficients
Granted: June 10, 2010
Application Number:
20100142607
A signaling system supports main and auxiliary communication channels between integrated circuits in the same direction over a single link. An equalizing transmitter applies appropriate filter coefficients to minimize the impact of intersymbol interference when transmitting the main data over a communication channel. The transmitter modulates at least one of the filter coefficients with the auxiliary data to induce apparent ISI in the transmitted signal. A main receiver ignores the…
Memory System Topologies Including A Buffer Device And An Integrated Circuit Memory Device
Granted: June 10, 2010
Application Number:
20100146199
Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address…
SINGLE-CLOCK, STROBELESS SIGNALING SYSTEM
Granted: June 10, 2010
Application Number:
20100146321
A signaling system includes a signaling path, a master device coupled to the signaling path, a slave device coupled to the signaling path, and a clock generator. The slave device includes timing circuitry to generate an internal clock signal having a phase offset relative to a clock signal supplied by the clock generator, the phase offset being determined at least in part by a signal propagation time on the signal path.
Adjusting Clock Error Across A Circuit Interface
Granted: June 3, 2010
Application Number:
20100135100
A system is provided with clock skew measurement and correction technology. A first circuit or memory controller 4 includes measuring circuits to measure relative timing or phase offsets of multiple clock signals of a second circuit or memory 6. One measuring circuit is configured for incremental changing of the phase of a transmitted test data sequence to measure and correct timing of a memory receiver circuit's quadrature clocks based on results of a data comparison of transmitted and…
BI-DIRECTIONAL INTERFACE CIRCUIT HAVING A SWITCHABLE CURRENT-SOURCE BIAS
Granted: June 3, 2010
Application Number:
20100135370
A bi-directional interface circuit includes a transmitter portion, a receiver portion, a current source bias circuit, and a switch. When the interface circuit is transmitting data, the switch steers the bias current generated by the current source bias circuit to the transmitter portion of the interface. When the interface is receiving data, the switch steers the bias current to the receiver portion of the interface. Thus, the current-source bias circuit is kept on regardless of whether…
Receiver with Clock Recovery Circuit and Adaptive Sample and Equalizer Timing
Granted: June 3, 2010
Application Number:
20100135378
A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the…
Reference Clock and Command Word Alignment
Granted: May 27, 2010
Application Number:
20100128542
A memory system includes a memory controller that issues command signals and a reference-clock signal to a memory device. The edge rate of the reference-clock signal is lower than the bit rate of the command signals, so the memory device multiplies the reference clock signal to develop a command-recovery clock signal with which to sample the incoming command signals. The memory controller issues the command signals as a series of multi-bit command words aligned with edges of the…
Memory System And Device With Serialized Data Transfer
Granted: May 27, 2010
Application Number:
20100131725
A memory system with serialized data transfer. The memory system includes within a memory controller and a plurality of memory devices. The memory controller receives a plurality of write data values from a host and outputs the write data values as respective serial streams of bits. Each of the memory devices receives at least one of the serial streams of bits from the memory controller and converts the serial stream of bits to a set of parallel bits for storage.
System Including Hierarchical Memory Modules Having Different Types Of Integrated Circuit Memory Devices
Granted: May 6, 2010
Application Number:
20100115191
A memory system is disclosed comprising a memory controller and a first set of volatile memory devices defining a first memory hierarchy. The first set of volatile memory devices are disposed on at least one first memory module, which is coupled to the memory controller in a daisy-chained configuration. A first integrated circuit buffer device is included on the module. The system has a second set of nonvolatile memory devices defining a second memory hierarchy. The second set of…
ADJUSTABLE WIDTH STROBE INTERFACE
Granted: April 29, 2010
Application Number:
20100103713
A memory system comprises a circuit board 40 including N data signal lines 60, 65 and at least two strobe signal lines 70, 75, and first and second memory devices 50, 55 secured to opposing surfaces 40a, 40b of the circuit board. Each memory device is coupled to a portion of the N data signal lines and to a portion of the at least two strobe signal lines such that the devices do not share any of the N data signal lines and such that the devices do not share any of the strobe signal…
PARTIAL RESPONSE DECISION-FEEDBACK EQUALIZATION WITH ADAPTATION BASED ON EDGE SAMPLES
Granted: April 29, 2010
Application Number:
20100103999
A device (102) implements data reception with edge-based partial response decision feedback equalization. In an example embodiment, the device implements a tap weight adapter circuit (114) that sets the tap weights that are used for adjustment of a received data signal (104). The tap weight adapter circuit (119) sets the tap weights based on previously determined data values and input from an edge analysis of the received data signal using a set of edge samplers. The edge analysis (116)…
Integrated Circuit Having Receiver Jitter Tolerance ("JTOL") Measurement
Granted: April 22, 2010
Application Number:
20100097071
An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.
PROCESSOR-MEMORY UNIT FOR USE IN SYSTEM-IN-PACKAGE AND SYSTEM-IN-MODULE DEVICES
Granted: April 22, 2010
Application Number:
20100100661
An apparatus and method for a processor-memory unit for use in system-in-package (SiP) and system-in-package (SiP) integrated circuit devices. The apparatus includes a processing module, a memory module and a programmable system module. The programmable system module is configured to function as an interface between the memory module and the processing module, or as an interface between the memory module and a testing device. The invention facilitates integration and testing of…
CLOCK AND DATA RECOVERY EMPLOYING PIECE-WISE ESTIMATION ON THE DERIVATIVE OF THE FREQUENCY
Granted: April 15, 2010
Application Number:
20100090732
A system and method for performing clock data recovery. The system sets the phase of a recovered clock signal 30 according to at least three estimates of the rate of change of an offset between the frequency of the data transmitter clock and the frequency of a receiver clock 15.
Low-Power Clock Generation and Distribution Circuitry
Granted: April 8, 2010
Application Number:
20100085100
A communication IC includes a power-efficient clock-distribution system. A control loop monitors and adjusts the peak and trough voltages of a clock signal. The clock signal can be adaptively adjusted to center the peak and trough voltages about the switching threshold voltage of a clock buffer. The voltage swing of the clock signal can thus be made small and, as a consequence, power efficient. The control loop can monitor and control more than one clock signal.
INJECTION-LOCKED CLOCK MULTIPLIER
Granted: April 8, 2010
Application Number:
20100085123
Embodiments of a clock circuit are described. This clock circuit includes an oscillator, which includes a resonance circuit having a resonance frequency, that outputs a first clock signal having a first frequency. Furthermore, a digital controller is coupled to the oscillator. This digital controller modifies the resonance frequency of the oscillator during a first mode of operation of the clock circuit, and the modifying is ceased during a second mode of operation of the clock circuit.…
SIGNAL LINES WITH INTERNAL AND EXTERNAL TERMINATION
Granted: March 25, 2010
Application Number:
20100073023
Embodiments of a memory controller are described. This memory controller communicates signals to a memory device via a signal line, which can be a data signal line or a command/address signal line. Termination of the signal line is divided between an external impedance outside of the memory controller and an internal impedance within the memory controller. The memory controller does not activate the external impedance prior to communicating the signals and, therefore, does not deactivate…
Apparatus for Data Recovery in a Synchronous Chip-to-Chip System
Granted: March 25, 2010
Application Number:
20100073047
An apparatus that reduces sampling errors for data communicated between devices uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling signal for sampling a data signal that was sent along with the timing reference signal. The data-sampling signal may be provided by adjustably delaying a clock signal according to the phase information acquired from the strobe signal. The data-sampling signal may also have an improved waveform…
