SELECTIVE REFRESH WITH SOFTWARE COMPONENTS
Granted: March 6, 2014
Application Number:
20140068172
A method of refreshing a memory is disclosed. The method includes accessing from active memory an active memory map. The active memory map is generated by software and identifies addresses corresponding to the active memory and associated refresh criteria for the addresses. The refresh criteria are evaluated for a portion of the active memory, and an operation initiated to refresh a portion of the active memory is based on the refresh criteria.
STACKED DRAM DEVICE AND METHOD OF MANUFACTURE
Granted: March 6, 2014
Application Number:
20140063887
A memory stack includes a number of memory dies including a master die and one or more slave dies. The slave die can be converted to a master die by further processing. The slave die includes a memory core having memory cell arrays. The slave die also includes first and second metal layers that form first and second distribution lines in the memory core, respectively. An interface circuit in the slave die is decoupled from the first and second metal layers.
DIGITAL PLL WITH DYNAMIC LOOP GAIN CONTROL
Granted: March 6, 2014
Application Number:
20140062549
The disclosed embodiments relate to a digital phase-locked loop (PLL) with dynamic gain control. This digital PLL includes a phase detector which receives a reference signal and a feedback signal as inputs and produces an output signal comprising up/down values. It also includes a digital loop filter which receives the phase-detector output signal as an input and produces an M-bit output signal. This digital loop filter is associated with a loop-parameter control unit (LPCU) which…
Binary Pixel Circuit Architecture
Granted: February 27, 2014
Application Number:
20140054446
An integrated-circuit image sensor that includes an array of pixel regions composed of binary pixel circuits. Each binary pixel circuit includes a binary amplifier having an input and an output. The binary amplifier generates a binary signal at the output in response to whether an input voltage at the input exceeds a switching threshold voltage level of the binary amplifier. A light-detecting element of the binary pixel circuit is coupled to the input of the binary amplifier.…
Memory with Alternative Command Interfaces
Granted: February 20, 2014
Application Number:
20140052934
A memory device or module selects between alternative command ports. Memory systems with memory modules incorporating such memory devices support point-to-point connectivity and efficient interconnect usage for different numbers of modules. The memory devices and modules can be of programmable data widths. Devices on the same module can be configured select different command ports to facilitate memory threading. Modules can likewise be configured to select different command ports for the…
MEMORY CONTROLLER RESPONSIVE TO LATENCY-SENSITIVE APPLICATIONS AND MIXED-GRANULARITY ACCESS REQUESTS
Granted: February 20, 2014
Application Number:
20140052906
A multi-channel memory controller (110, 600) may be dynamically re-architected to schedule low and high-latency memory access requests differently (FIG. 12) in order to make more efficient use of memory resources and improve overall performance. Data may be duplicated or “cloned” in a clone area (612) of one or more channels of a multi-channel or module threaded memory (610), the clone area being reserved by the memory controller. Cloning information is stored in a clone mapping…
POWER SAVING DRIVER DESIGN
Granted: February 13, 2014
Application Number:
20140043069
In an asymmetrically terminated communication system, the power consumed to transmit a particular bit value is adjusted based on whether the bit being output is the second, third, fourth, etc. consecutive bit with the same value after a transition to output the particular bit value. The adjustment of the power consumed to transmit the two or more consecutive bits with the same value may be made by adjusting the driver strength during the second, or subsequent, consecutive bits with the…
CONFIGURABLE, ERROR-TOLERANT MEMORY CONTROL
Granted: February 13, 2014
Application Number:
20140047306
Configurable, error-tolerant communication of memory control information between components of a memory system. A controller component and memory component each have a variable-width command/address (CA) interface that operates in conjunction with an error detection/correction (EDC) channel to enable a variable level of error detection and correction with respect to command/address information conveyed between the two components as the widths of the CA interfaces are adjusted.
MEMORY MODULE THREADING WITH STAGGERED DATA TRANSFERS
Granted: February 13, 2014
Application Number:
20140047155
A method of transferring data between a memory controller and at least one memory module via a primary data bus having a primary data bus width is disclosed. The method includes accessing a first one of a memory device group via a corresponding data bus path in response to a threaded memory request from the memory controller. The accessing results in data groups collectively forming a first data thread transferred across a corresponding secondary data bus path. Transfer of the first data…
INTEGRATED CIRCUIT HAVING A MULTIPLYING INJECTION-LOCKED OSCILLATOR
Granted: February 13, 2014
Application Number:
20140043105
Methods and apparatuses featuring a multiplying injection-locked oscillator are described. Some embodiments include a pulse-generator-and-injector and one or more injection-locked oscillators. The outputs of the pulse-generator-and-injector can be injected into corresponding injection points of an injection-locked oscillator. In embodiments that include multiple injection-locked oscillators, the outputs of each injection-locked oscillator can be injected into the corresponding injection…
IMAGE SENSOR WITH A SPLIT-COUNTER ARCHITECTURE
Granted: February 6, 2014
Application Number:
20140034809
A split-counter architecture is implemented within an image sensor system. A first counter within an image sensor region counts image data from pixel regions within the image sensor region, and outputs the most significant bits of the image data to a second counter external to the image sensor region, reducing the bandwidth required between the image sensor region and the second counter, and reducing the size of the counters within the image sensor region.
Memory Component with Pattern Register Circuitry to Provide Data Patterns for Calibration
Granted: January 30, 2014
Application Number:
20140032830
A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a…
TIMING CALIBRATION FOR MULTIMODE I/O SYSTEMS
Granted: January 16, 2014
Application Number:
20140019792
Integrated circuit devices that operate in different modes. In a low data rate mode, data is transferred between the integrated circuit devices at a low data rate, or no data is transferred at all. In a high data rate mode, data is transferred between integrated circuit devices at a high data rate. A transition mode facilitates the transition from the low data rate mode to the high data rate mode. During the transition mode data is transferred between the integrated circuit devices at an…
EDGE BASED PARTIAL RESPONSE EQUALIZATION
Granted: January 16, 2014
Application Number:
20140016692
A device implements data reception with edge-based partial response decision feedback equalization. In an example embodiment, the device implements a tap weight adapter circuit that sets the tap weights that are used for adjustment of a received data signal. The tap weight adapter circuit sets the tap weights based on previously determined data values and input from an edge analysis of the received data signal using a set of edge samplers. The edge analysis may include adjusting the…
MULTI-COLUMN ADDRESSING MODE MEMORY SYSTEM INCLUDING AN INTEGRATED CIRCUIT MEMORY DEVICE
Granted: January 2, 2014
Application Number:
20140003131
A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first…
ON-DIE TERMINATION
Granted: January 2, 2014
Application Number:
20140002131
Local on-die termination controllers for effecting termination of a high-speed signaling links simultaneously engage on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link. A termination control bus is coupled to memory devices on a module, and provides for peer-to-peer communication of termination control signals.
ITERATIVE INTERFERENCE SUPPRESSION USING MIXED FEEDBACK WEIGHTS AND STABILIZING STEP SIZES
Granted: December 26, 2013
Application Number:
20130343498
A receiver is configured for canceling intra-cell and inter-cell interference in coded, multiple-access, spread-spectrum transmissions that propagate through frequency-selective communication channels. The receiver employs iterative symbol-estimate weighting, subtractive cancellation with a stabilizing step-size, and mixed-decision symbol estimate. Receiver embodiments may be implemented explicitly in software of programmed hardware, or implicitly in standard Rake-based hardware either…
MEMORY COMPONENTS AND CONTROLLERS THAT CALIBRATE MULTIPHASE SYNCHRONOUS TIMING REFERENCES
Granted: December 26, 2013
Application Number:
20130346721
A first timing reference signal and a second timing reference signal are sent to a memory device. The second timing reference signal has approximately a quadrature phase relationship with respect to the first timing reference signal. A plurality of serial data patterns are received from the memory device. The transitions of the first timing reference and the second timing reference determining when transitions occur between the bits of the plurality of data patterns. Timing indicators…
Memory Component with Pattern Register Circuitry to Provide Data Patterns for Calibration
Granted: December 26, 2013
Application Number:
20130346685
A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a…
Generating Interface Adjustment Signals in a Device-To-Device Interconnection System
Granted: December 26, 2013
Application Number:
20130346663
Described are a system and method to control interface timing and/or voltage operations of signals transmitted between devices. A processor may be coupled through one or more bus interfaces of a bus to one or more corresponding interface timing and/or voltage comparison circuits and corresponding interface timing and/or voltage adjustment circuits.
