NON-VOLATILE MEMORY WITH EFFICIENT TESTING DURING ERASE
Granted: August 17, 2023
Application Number:
20230260582
When erasing multiple sub-blocks of a block, erase verify is performed for memory cells connected to even word lines to generate even results and for memory cells connected to odd word lines to generate odd results. The even results and the odd results are used to determine that the erase verify process successfully completed. For each NAND string of a first sub-block, a last even result for the NAND string is compared to a last odd result for the NAND string. Despite the determination…
NON-VOLATILE STORAGE SYSTEM WITH PROGRAM EXECUTION DECOUPLED FROM DATALOAD
Granted: August 17, 2023
Application Number:
20230259300
Technology is disclosed for a non-volatile memory system that decouples dataload from program execution. A memory controller transfers data for a program operation and issues a first type of program execution command. When in a coupled mode, the die programs the data in response to the first type of program execution command. When in a decoupled mode, rather than program the data into non-volatile memory cells the die enters a wait state. Optionally, the memory controller can instruct…
CURRENT MIRROR CIRCUITS
Granted: August 17, 2023
Application Number:
20230259149
A circuit is provided that includes a first transistor having a first terminal, a second terminal and a third terminal, and a second transistor comprising a first terminal, a second terminal and a third terminal. The first terminal of the first transistor comprises an input terminal of the circuit, the second terminal of the first transistor is coupled to a power supply bus, and the first transistor conducts a first current. The first terminal of the first transistor comprises an output…
PRE-POSITION DUMMY WORD LINE TO FACILITATE WRITE ERASE CAPABILITY OF MEMORY APPARATUS
Granted: August 10, 2023
Application Number:
20230253056
A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines including a dummy word line and other data word lines. The memory cells are disposed in memory holes and configured to retain a threshold voltage. A control means is coupled to the word lines and the memory holes and is configured to determine whether one of the word lines being programmed in a program operation is a particular one of the word lines adjacent the dummy word…
NEIGHBOR BIT LINE COUPLING ENHANCED GATE-INDUCED DRAIN LEAKAGE ERASE FOR MEMORY APPARATUS WITH ON-PITCH SEMI-CIRCLE DRAIN SIDE SELECT GATE TECHNOLOGY
Granted: August 10, 2023
Application Number:
20230253053
A memory apparatus and method of operation are provided. The memory apparatus includes memory cells connected to word lines and disposed in memory holes organized in rows grouped in strings. The memory cells are configured to retain a threshold voltage. The rows include full circle rows and semi-circle rows in which the memory holes are partially cut by a slit half etch. The memory holes of the semi-circle rows are coupled semi-circle bit lines and the memory holes of the full circle…
CELSRC VOLTAGE SEPARATION BETWEEN SLC AND XLC FOR SLC PROGRAM AVERAGE ICC REDUCTION
Granted: August 10, 2023
Application Number:
20230253049
A non-volatile semiconductor memory device, described herein, comprises a bit line, a source line, a memory string comprising a plurality of memory cells connected in series between the source line and the bit line, and control circuitry coupled to the plurality of memory cells, the source line, and the bit line. The control circuitry is configured to: determine if a program operation is a single-bit program operation or multi-bit program operation; in response to the determination,…
VARIABLE PROGRAMMING CLOCKS DURING A MULTI-STAGE PROGRAMMING OPERATION IN A NAND MEMORY DEVICE
Granted: August 10, 2023
Application Number:
20230253048
The memory device includes an array of memory cells, which are configured to retain multiple bits per memory cell, arranged in a plurality of word lines. A controller is configured to program the memory cells of a selected word line in a first programming pass. The first programming pass includes a plurality of programming pulses, each including the application of a programming voltage Vpgm by the controller to a control gate of the selected word line for a first duration. The controller…
PROGRAM VOLTAGE DEPENDENT PROGRAM SOURCE LEVELS
Granted: August 10, 2023
Application Number:
20230253047
A non-volatile semiconductor memory device, described herein, comprises non-volatile storage elements and one or more control circuits in communication with the non-volatile storage elements. The one or more control circuits are configured to, during a program iteration of a program operation, determine whether a program voltage level of the program iteration exceeds a threshold program voltage level and in response to the determination, identify a set of voltage levels to apply to a…
MIXING NORMAL AND REVERSE ORDER PROGRAMMING IN NAND MEMORY DEVICES
Granted: August 10, 2023
Application Number:
20230253046
The memory device includes a plurality of dies, and each die includes a plurality of blocks with a plurality of word lines. Some of the word lines are arranged in a plurality of exclusive OR (XOR) sets with each XOR set containing word lines in the same positions across the plurality of dies. The memory device further includes a controller that is configured to program the word lines of the blocks of at least one of the dies in a first programming direction. The controller is further…
NON-VOLATILE MEMORY WITH ZONE BASED PROGRAM SPEED ADJUSTMENT
Granted: August 3, 2023
Application Number:
20230245706
In order to decrease the width of threshold voltage distributions of programmed memory cells without unreasonably increasing the time needed to complete programming, a non-volatile memory uses a zone based program speed adjustment. The non-volatile memory starts programming a first set of the non-volatile memory cells until a minimum number of memory cells of the first set of non-volatile memory cells reach a first threshold voltage. In response to the minimum number of memory cells…
SUB-BLOCK MODE FOR NON-VOLATILE MEMORY
Granted: July 27, 2023
Application Number:
20230238062
The memory device includes a block with a plurality of memory cells arranged in a plurality of data word lines, which are arranged in sub-blocks that are not separated from one another by physical joints or by dummy word lines. A controller is configured to erase the memory cells of a selected sub-block of the plurality of sub-blocks without erasing the memory cells of the unselected sub-blocks. The controller reads data of the edge one word lines of the unselected sub-blocks adjacent…
HYBRID MULTI-BLOCK ERASE TECHNIQUE TO IMPROVE ERASE SPEED IN A MEMORY DEVICE
Granted: July 13, 2023
Application Number:
20230223087
The memory device includes a plurality of memory cells arranged in a plurality of blocks, which are arranged in at least one plane. A controller is in electrical communication with the plurality of memory cells. The controller is configured to define a multi-block group that includes at least two blocks to be erased. The controller is further configured to simultaneously apply at least one erase pulse to the multi-block group. The controller is further configured to individually and…
VOLTAGE KICK FOR IMPROVED ERASE EFFICIENCY IN A MEMORY DEVICE
Granted: July 13, 2023
Application Number:
20230223086
The memory device includes a plurality of memory cell that arranged in an array, which includes a plurality of channels that are in electrical communication with a source line. The memory device also includes a controller that is configured to erase the memory cells in at least one erase pulse. During the at least one erase pulse, the controller is configured to drive the source line to an elevated voltage that is equal to an erase voltage Vera plus a kick voltage V_kick for a duration…
WORD LINE ZONE DEPENDENT PRE-CHARGE VOLTAGE
Granted: July 13, 2023
Application Number:
20230223084
A memory device that uses different programming parameters base on the word line(s) to be programmed is described. The programming parameter PROGSRC_PCH provides a pre-charge voltage to physical word lines. In some instances, the PROGSRC_PCH voltage is decoupled, and a new PROGSRC_PCH represents an adjusted (e.g., increased) pre-charge voltage for a certain physical word line or word line zone (i.e., predetermined group of word lines). Using different PROGSRC_PCH voltages can limit or…
NON-VOLATILE MEMORY WITH EFFICIENT SIGNAL ROUTING
Granted: June 29, 2023
Application Number:
20230207504
An integrated memory assembly comprises a control die bonded to a memory die. The memory die includes multiple non-volatile memory structures (e.g., planes, arrays, groups of blocks, etc.), each comprising a stack of alternating conductive and dielectric layers forming staircases at one or more edges of the non-volatile memory structures. The non-volatile memory structures are positioned with gaps between the non-volatile memory structures such that the gaps separate the staircases of…
SENSE AMPLIFIER STRUCTURE FOR NON-VOLATILE MEMORY WITH NEIGHBOR BIT LINE LOCAL DATA BUS DATA TRANSFER
Granted: June 29, 2023
Application Number:
20230207022
A local data bus of a sense amplifier associated with one bit line is used to perform logical operations for a sensing operation performed by another sense amplifier associated with a different bit line. Each sense amplifier circuit includes a sensing node that is pre-charged, then discharged through a selected memory cell and a local data bus with a number of data latches connected. Target program data can be stored in the latches and combined in logical combinations with the sensed…
STRING OR BLOCK OR DIE LEVEL DEPENDENT SOURCE LINE VOLTAGE FOR NEIGHBOR DRAIN SIDE SELECT GATE INTERFERENCE COMPENSATION
Granted: June 29, 2023
Application Number:
20230207021
A memory apparatus and method of operation are provided. The memory apparatus includes memory cells connected to word lines and disposed in memory holes. The memory cells are connected in series between a drain-side select gate transistor on a drain-side and connected to one of a plurality of bit lines and a source line on a source-side. A control means is configured to apply a first and a second select gate voltage to the drain-side select gate transistor while applying a predetermined…
NON-VOLATILE MEMORY WITH DIFFERENTIAL TEMPERATURE COMPENSATION FOR BULK PROGRAMMING
Granted: June 22, 2023
Application Number:
20230197168
A system has been described that performs differential temperature compensation based on a differential between the temperature at time of programming and temperature at time of reading for a set of data. Differential temperature compensation is useful for bulk programming/reading (e.g., many pages of data) and/or programming/reading super pages of data (multiple pages residing on different memory die).
SYSTEMS AND METHODS FOR ADAPTING SENSE TIME
Granted: June 22, 2023
Application Number:
20230197174
A memory device with adaptive sense time tables is disclosed. In order to maintain a desired (initial or preset) threshold voltage distribution, the sense time is adjusted as the program-erase cycle count increases. The program-erase cycle process tends to wear down memory cells, causing the QPW window to expand and the threshold voltage to widen. However, by adjusting (i.e., reducing) the sense time for increased program-erase cycles, the QPW window and the threshold voltage can be at…
EDGE WORD LINE CONCURRENT PROGRAMMING WITH VERIFY FOR MEMORY APPARATUS WITH ON-PITCH SEMI-CIRCLE DRAIN SIDE SELECT GATE TECHNOLOGY
Granted: June 22, 2023
Application Number:
20230197172
A memory apparatus and method of operation are provided. The memory apparatus includes memory cells connected to one of a plurality of word lines including an edge word line and a plurality of other data word lines. The memory cells are disposed in memory holes organized in rows grouped in a plurality of strings. The rows include full circle rows and semi-circle rows. A control means is configured to program the memory cells connected to the edge word line and in the semi-circle rows of…
