NON-VOLATILE MEMORY WITH DIFFERENTIAL TEMPERATURE COMPENSATION FOR BULK PROGRAMMING
Granted: June 22, 2023
Application Number:
20230197168
A system has been described that performs differential temperature compensation based on a differential between the temperature at time of programming and temperature at time of reading for a set of data. Differential temperature compensation is useful for bulk programming/reading (e.g., many pages of data) and/or programming/reading super pages of data (multiple pages residing on different memory die).
SIMULATING MEMORY CELL SENSING FOR TESTING SENSING CIRCUITRY
Granted: June 15, 2023
Application Number:
20230187014
Technology is disclosed herein for testing circuitry that controls memory operations in a memory structure having non-volatile memory cells. The testing of the circuitry can be performed without the memory structure. The memory structure may reside on one semiconductor die, with sense blocks and a control circuit on another semiconductor die. The control circuit is able to perform die level control of memory operations in the memory structure. The control circuit may control the sense…
NON-VOLATILE MEMORY WITH DATA REFRESH
Granted: June 15, 2023
Application Number:
20230187000
A memory system identifies memory cells connected to a common word line that have had their threshold voltage unintentionally drift lower than programmed by determining whether memory cells meet two criteria: (1) the memory cells have threshold voltages within an offset of a read compare voltage of a data state; and (2) adjacent memory cells (connected to word lines that are adjacent to the common word line) are in one or more low data states. For those memory cells meeting the two…
METHOD TO FIX CUMULATIVE READ INDUCED DRAIN SIDE SELECT GATE DOWNSHIFT IN MEMORY APPARATUS WITH ON-PITCH DRAIN SIDE SELECT GATE
Granted: June 15, 2023
Application Number:
20230186998
A memory apparatus and method of operation are provided. The memory apparatus includes memory cells configured to retain a threshold voltage. The memory cells are connected to one of a plurality of word lines and are arranged in strings comprising a plurality of blocks. A control means is coupled to the plurality of word lines and the strings and is configured to periodically determine a read frequency metric associated with a plurality of read operations of one of the plurality of…
NON-VOLATILE MEMORY WITH DIFFERENTIAL TEMPERATURE COMPENSATION FOR SUPER PAGE PROGRAMMING
Granted: June 15, 2023
Application Number:
20230186996
A system has been described that performs differential temperature compensation based on a differential between the temperature at time of programming and temperature at time of reading for a set of data. Differential temperature compensation is useful for bulk programming/reading (e.g., many pages of data) and/or programming/reading super pages of data (multiple pages residing on different memory die).
CONTROL GATE SIGNAL FOR DATA RETENTION IN NONVOLATILE MEMORY
Granted: June 15, 2023
Application Number:
20230186993
The nonvolatile memory includes a plurality of nonvolatile memory cells configured to store multiple data states; a word line connected to a control gate of at least one of the plurality of non-volatile memory cells; a control gate line to supply a control gate signal; a word line switch connected between the word line and the control gate line to control the potential applied to the word line from the control gate line; and a memory controller circuit. The memory controller circuit is…
SOFT ERASE PROCESS DURING PROGRAMMING OF NON-VOLATILE MEMORY
Granted: May 18, 2023
Application Number:
20230154541
Programming a plurality of non-volatile memory cells includes performing a soft erase process during the programming. The soft erase process includes pre-charging channels of the memory cells and performing an erase operation subsequent to the pre-charging while the channels are at one or more elevated voltages at least partially due to the pre-charging.
TECHNIQUES FOR ERASING THE MEMORY CELLS OF EDGE WORD LINES
Granted: May 18, 2023
Application Number:
20230154550
A method of erasing memory cells in a memory device is provided. The method includes grouping a plurality of word lines into a first group, which does not include edge word lines, and a second group, which does include edge word lines. An erase operation is performed on the memory cells of the first and second groups until erase-verify of the memory cells of the first group passes. It is then determined if further erase of the memory cells of the second group is necessary. In response to…
NON-VOLATILE MEMORY WITH STAGGERED RAMP DOWN AT THE END OF PRE-CHARGING
Granted: May 18, 2023
Application Number:
20230154538
In order to inhibit memory cells from programming and mitigate program disturb, the memory pre-charges channels of NAND strings connected to a common set of control lines by applying positive voltages to the control lines and applying voltages to a source line and bit lines connected to the NAND strings. The control lines include word lines and select lines. The word lines include an edge word line. The memory ramps down the positive voltages applied to the control lines, including…
SYSTEMS AND METHODS FOR STAGGERING READ OPERATION OF SUB-BLOCKS
Granted: May 11, 2023
Application Number:
20230146549
A memory device with one or more planes having sub-blocks is disclosed. The memory device may further include a voltage switch transistor for each of sub-blocks. Additionally, the memory device may further include a row decoder for each of sub-blocks. As a result, an operation to two sub-blocks can be performed at different times. For example, using a row decoder and voltage switch transistor, a sub-block can be initially read, followed by a subsequent read of another sub-block using a…
MODELLING AND PREDICTION SYSTEM WITH AUTO MACHINE LEARNING IN THE PRODUCTION OF MEMORY DEVICES
Granted: May 11, 2023
Application Number:
20230142936
To provide more test data during the manufacture of non-volatile memories and other integrated circuits, machine learning is used to generate virtual test values. Virtual test results are interpolated for one set of tests for devices on which the test is not performed based on correlations with other sets of tests. In one example, machine learning determines a correlation study between bad block values determined at die sort and photo-limited yield (PLY) values determined inline during…
MODELLING AND PREDICTION SYSTEM WITH AUTO MACHINE LEARNING IN THE PRODUCTION OF MEMORY DEVICES
Granted: May 11, 2023
Application Number:
20230142936
To provide more test data during the manufacture of non-volatile memories and other integrated circuits, machine learning is used to generate virtual test values. Virtual test results are interpolated for one set of tests for devices on which the test is not performed based on correlations with other sets of tests. In one example, machine learning determines a correlation study between bad block values determined at die sort and photo-limited yield (PLY) values determined inline during…
SYSTEMS AND METHODS FOR STAGGERING READ OPERATION OF SUB-BLOCKS
Granted: May 11, 2023
Application Number:
20230146549
A memory device with one or more planes having sub-blocks is disclosed. The memory device may further include a voltage switch transistor for each of sub-blocks. Additionally, the memory device may further include a row decoder for each of sub-blocks. As a result, an operation to two sub-blocks can be performed at different times. For example, using a row decoder and voltage switch transistor, a sub-block can be initially read, followed by a subsequent read of another sub-block using a…
PROACTIVE EDGE WORD LINE LEAK DETECTION FOR MEMORY APPARATUS WITH ON-PITCH SEMI-CIRCLE DRAIN SIDE SELECT GATE TECHNOLOGY
Granted: April 27, 2023
Application Number:
20230125748
A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to one of a plurality of word lines and arranged in strings and configured to retain a threshold voltage. A control means is coupled to the plurality of word lines and the strings. The control means is configured to apply a primary predetermined voltage to a primary location of the memory apparatus following an erase operation of the memory cells while simultaneously applying a…
PSEUDO MULTI-PLANE READ METHODS AND APPARATUS FOR NON-VOLATILE MEMORY DEVICES
Granted: April 27, 2023
Application Number:
20230131500
An apparatus includes a control circuit and a plurality of non-volatile memory cells arranged in a plane of a memory die. The plane includes a first word line including a first word line portion coupled to a corresponding first group of the non-volatile memory cells, and a second word line including a second word line portion coupled to a corresponding second group of the non-volatile memory cells, the second word line different from the first word line. The control circuit is configured…
DATA CONVERSION WITH DATA PATH CIRCUITS FOR USE IN DOUBLE SENSE AMP ARCHITECTURE WITH FRACTIONAL BIT ASSIGNMENT IN NON-VOLATILE MEMORY STRUCTURES
Granted: April 27, 2023
Application Number:
20230131117
A method for programming a non-volatile memory structure, comprises initiating a two-dimensional fractional number of bits-per-cell programming scheme of a plurality of memory cells, wherein the memory structure comprises: (1) a first memory array comprising a first population of memory cells and the associated peripheral circuitry disposed below the first population of cells, (2) a second memory array positioned above the first memory array and comprising a second population of memory…
SYSTEMS AND METHODS FOR RETAINING INFLIGHT DATA DURING A POWER LOSS EVENT
Granted: April 27, 2023
Application Number:
20230129097
Memory devices, or memory systems, described herein may include a controller (e.g., SSD controller) and a NAND memory device for storing inflight data. When the power loss event occurs, a memory system maintains (i.e., not un-select) the existing memory block being programmed at the time of power loss. The existing program operation at the event of power loss can be suspended by controller. The inflight data can be re-sent by controller directly to NAND latches, when power loss event was…
POSITIVE TCO VOLTAGE TO DUMMY SELECT TRANSISTORS IN 3D MEMORY
Granted: April 27, 2023
Application Number:
20230128177
Technology is disclosed for applying a positive temperature coefficient (Tco) voltage to a control terminal of a dummy select transistor. The dummy select transistor resides on a NAND string having non-volatile memory cells and a regular select transistor. The dummy select transistor is typically ON (or conductive) during memory operations such as selected string program, read, and verify. In an aspect, the positive Tco voltage is applied to the control terminal of a dummy select…
SYSTEMS AND METHODS FOR DYNAMICALLY SENSING A MEMORY BLOCK
Granted: April 27, 2023
Application Number:
20230126422
A memory device that dynamically adjusts the sense time to read an open block of a memory block is disclosed. The adjusted sense time is based upon various considerations, including the sense time of the closed block equivalent and the openness of the open block. This allows the memory device to maintain a fixed Vt as well as reduce failed bit count, i.e., read errors due to an insufficient sense time. Also, the dynamic adjustment of sense time can optimize system performance and…
COMPUTATION OF DISCRETE FOURIER TRANSFORMATION (DFT) USING NON-VOLATILE MEMORY ARRAYS
Granted: April 27, 2023
Application Number:
20230126357
A non-volatile memory device is configured for in-memory computation of discrete Fourier transformations and their inverses. The real and imaginary components of the twiddle factors are stored as conductance values of memory cells in non-volatile memory arrays having a cross-point structure. The real and imaginary components of inputs are encoded as word line voltages applied to the arrays. Positive and negative valued components of the twiddle factors are stored separately and positive…
