SYSTEMS AND METHODS FOR DYNAMICALLY SENSING A MEMORY BLOCK
Granted: April 27, 2023
Application Number:
20230126422
A memory device that dynamically adjusts the sense time to read an open block of a memory block is disclosed. The adjusted sense time is based upon various considerations, including the sense time of the closed block equivalent and the openness of the open block. This allows the memory device to maintain a fixed Vt as well as reduce failed bit count, i.e., read errors due to an insufficient sense time. Also, the dynamic adjustment of sense time can optimize system performance and…
COMPUTATION OF DISCRETE FOURIER TRANSFORMATION (DFT) USING NON-VOLATILE MEMORY ARRAYS
Granted: April 27, 2023
Application Number:
20230126357
A non-volatile memory device is configured for in-memory computation of discrete Fourier transformations and their inverses. The real and imaginary components of the twiddle factors are stored as conductance values of memory cells in non-volatile memory arrays having a cross-point structure. The real and imaginary components of inputs are encoded as word line voltages applied to the arrays. Positive and negative valued components of the twiddle factors are stored separately and positive…
PROACTIVE EDGE WORD LINE LEAK DETECTION FOR MEMORY APPARATUS WITH ON-PITCH SEMI-CIRCLE DRAIN SIDE SELECT GATE TECHNOLOGY
Granted: April 27, 2023
Application Number:
20230125748
A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to one of a plurality of word lines and arranged in strings and configured to retain a threshold voltage. A control means is coupled to the plurality of word lines and the strings. The control means is configured to apply a primary predetermined voltage to a primary location of the memory apparatus following an erase operation of the memory cells while simultaneously applying a…
VARIABLE PROGRAMMING VOLTAGE STEP SIZE CONTROL DURING PROGRAMMING OF A MEMORY DEVICE
Granted: April 20, 2023
Application Number:
20230124371
The memory device includes a control circuitry that is communicatively coupled to memory cells are arranged in a plurality of word lines. The control circuitry is configured to perform a first programming pass on a selected word line. The first programming pass includes a plurality of programming loops, each of which includes the application of a programming pulse (Vpgm). The programming pulse voltage is increased between programming loops of the first programming pass by a step size.…
NON-VOLATILE MEMORY WITH ADJUSTED BIT LINE VOLTAGE DURING VERIFY
Granted: April 20, 2023
Application Number:
20230120352
A control circuit connected to non-volatile memory cells applies a programming signal to a plurality of the non-volatile memory cells in order to program the plurality of the non-volatile memory cells to a set of data states. The control circuit performs program verification for the non-volatile memory cells, including applying bit line voltages during program verification based on word line position and data state being verified.
SMART RE-USE OF PARITY BUFFER
Granted: April 13, 2023
Application Number:
20230112636
Technology is disclosed herein for efficient use of volatile memory that is used for accumulating parity data of user data being written to non-volatile memory cells. A memory controller may replace primary parity in a first portion of a parity buffer with data other than primary parity while a second portion of the buffer is still being used to store the primary parity. Therefore, the memory controller smartly re-uses the parity buffer, which makes efficient use of the volatile memory.…
DOUBLE SENSE AMP AND FRACTIONAL BIT ASSIGNMENT IN NON-VOLATILE MEMORY STRUCTURES
Granted: April 13, 2023
Application Number:
20230110995
A method for programming a non-volatile memory structure, wherein the method comprises initiating a two-dimensional fractional number of bits-per-cell programming scheme with respect to at least a first memory cell and a second memory cell of a plurality of memory cells of the memory structure, wherein the memory structure comprises: (1) a first memory array that comprises a first population of the plurality of memory cells and associated peripheral circuitry disposed below the first…
MTIGATING NEIGHBOR INTERFERENCE TO SELECT GATES IN 3D MEMORY
Granted: March 30, 2023
Application Number:
20230101019
Technology for mitigating interference to select transistors in 3D memory is disclosed. In one aspect, a control circuit pre-charges a first set of bit lines to a first voltage and pre-charges a second set of bit lines to a second voltage greater than the first voltage. The control circuit may increase the voltage on the first set of bit lines to the second voltage while the second set of bit lines are floating to couple up the voltages on the second set of bit lines to a voltage greater…
PROACTIVE REFRESH OF EDGE DATA WORD LINE FOR SEMI-CIRCLE DRAIN SIDE SELECT GATE
Granted: March 30, 2023
Application Number:
20230102668
A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to one of a plurality of word lines including at least one edge word line and a plurality of other data word lines. The memory cells are arranged in strings and configured to retain a threshold voltage corresponding to one of a plurality of data states. The memory apparatus also includes a control means coupled to the plurality of word lines and the strings. The control means is…
PROGRAMMABLE ECC FOR MRAM MIXED-READ SCHEME
Granted: March 30, 2023
Application Number:
20230101414
Technology is disclosed for a fast ECC engine for a mixed read of MRAM cells. A codeword read from MRAM cells using a referenced read is decoded using a first ECC mode. If decoding passes, results are provided to a host. If decoding fails, a self-referenced read (SRR) is performed. The data read using the SRR is decoded with a second ECC mode that is capable of correcting a greater number of bits than the first ECC mode. The second ECC mode may have a higher mis-correction rate than the…
MIXED CURRENT-FORCED READ SCHEME FOR RERAM ARRAY WITH SELECTOR
Granted: March 30, 2023
Application Number:
20230100600
Technology for reading reversible resistivity cells in a memory array when using a current-force read is disclosed. The memory cells are first read using a current-force referenced read. If the current-force referenced read is successful, then results of the current-force referenced read are returned. If the current-force referenced read is unsuccessful, then a current-force self-referenced read (SRR) is performed and results of the current-force SRR are returned. The current-force…
SECONDARY CROSS-COUPLING EFFECT IN MEMORY APPARATUS WITH SEMICIRCLE DRAIN SIDE SELECT GATE AND COUNTERMEASURE
Granted: March 30, 2023
Application Number:
20230097040
A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and arranged in strings. The memory cells are configured to retain a threshold voltage corresponding to memory states. Each one of the strings has drain-side select gate transistors on a drain-side of the one of the strings including top drain-side select gate transistors connected to bit lines and coupled to the memory cells of the-one of the strings. A control means is…
PROGRAMMING TECHNIQUES FOR MEMORY DEVICES HAVING PARTIAL DRAIN-SIDE SELECT GATES
Granted: March 30, 2023
Application Number:
20230095757
A method of operating a memory device. The method includes the step of preparing a memory device that includes a first group of the memory holes with full SGD transistors and a second group of the memory holes with partial SGD transistors. The second group includes both a set of selected partial SGD transistors and a set of unselected partial SGD transistors. The method proceeds with electrically floating a first unselected partial SGD transistor of the set of unselected partial SGD…
ON-THE-FLY MULTIPLEXING SCHEME FOR COMPRESSED SOFT BIT DATA IN NON-VOLATILE MEMORIES
Granted: March 30, 2023
Application Number:
20230095127
For a non-volatile memory that uses hard bit and soft bit data in error correction operations, to reduce the amount of soft bit data that needs to be transferred from a memory to the controller and improve memory system performance, the soft bit data can be compressed before transfer. After the soft bit data is read and stored into the internal data latches associated with the sense amplifiers, it is compressed within these internal data latches. The compressed soft bit data can then be…
USE OF DATA LATCHES FOR PLANE LEVEL COMPRESSION OF SOFT BIT DATA IN NON-VOLATILE MEMORIES
Granted: March 23, 2023
Application Number:
20230085776
For a non-volatile memory that uses hard bit and soft bit data in error correction operations, to reduce the amount of soft bit data that needs to be transferred from a memory to the controller and improve memory system performance, the soft bit data can be compressed before transfer. After the soft bit data is read and stored into the internal data latches associated with the sense amplifiers, it is compressed within these internal data latches. The compressed soft bit data can then be…
EFFICIENT SENSING OF SOFT BIT DATA FOR NON-VOLATILE MEMORY
Granted: March 16, 2023
Application Number:
20230077517
A non-volatile memory combines a hard bit and a soft bit read into a single, efficient soft sense sequence by using two sense per state level to improve read time efficiency. Rather than a standard hard bit read, where two soft bit reads are performed, offset above and below the hard bit read value, the hard bit read is shifted so that it reliable senses one state but less reliably senses the other state and soft bit data is only determined for the less reliably sensed state. This…
VERTICAL COMPRESSION SCHEME FOR COMPRESSED SOFT BIT DATA IN NON-VOLATILE MEMORIES WITH DATA LATCH GROUPS
Granted: March 16, 2023
Application Number:
20230085405
For a non-volatile memory that uses hard bit and soft bit data in error correction operations, to reduce the amount of soft bit data that needs to be transferred from a memory to the controller and improve memory system performance, the soft bit data can be compressed before transfer. After the soft bit data is read and stored into the internal data latches associated with the sense amplifiers, it is compressed within these internal data latches. The compressed soft bit data can then be…
USE OF DATA LATCHES FOR COMPRESSION OF SOFT BIT DATA IN NON-VOLATILE MEMORIES
Granted: March 16, 2023
Application Number:
20230081623
For a non-volatile memory that uses hard bit and soft bit data in error correction operations, to reduce the amount of soft bit data that needs to be transferred from a memory to the controller and improve memory system performance, the soft bit data can be compressed before transfer. After the soft bit data is read and stored into the internal data latches associated with the sense amplifiers, it is compressed within these internal data latches. The compressed soft bit data can then be…
ARCHITECTURE AND DATA PATH OPTIONS FOR COMPRESSION OF SOFT BIT DATA IN NON-VOLATILE MEMORIES
Granted: March 16, 2023
Application Number:
20230080999
For a non-volatile memory that uses hard bit and a soft bit data in error correction operations, architectures are introduced for the compression of the soft bit data to reduce the amount of data transferred over the memory's input-output interface. For a memory device with multiple planes of memory cells, the internal global data bus is segmented and a data compression circuit associated with each segment. This allows soft bit data from a cache buffer of a plane using one segment to…
PROGRAMMING TECHNIQUES TO IMPROVE PROGRAMMING TIME AND REDUCE PROGRAMMING ERRORS
Granted: March 16, 2023
Application Number:
20230078456
A memory device including an array of memory cells arranged in a plurality of word lines is provided. A control circuitry is configured to program the memory cells of a selected word line to a plurality of leading data states in a plurality of programming loops that include programming and verify pulses. The control circuitry is also configured to count a total number of programming loops during programming of the selected word line. The control circuitry is also configured to program at…
