EFFICIENT SENSING OF SOFT BIT DATA FOR NON-VOLATILE MEMORY
Granted: March 16, 2023
Application Number:
20230077517
A non-volatile memory combines a hard bit and a soft bit read into a single, efficient soft sense sequence by using two sense per state level to improve read time efficiency. Rather than a standard hard bit read, where two soft bit reads are performed, offset above and below the hard bit read value, the hard bit read is shifted so that it reliable senses one state but less reliably senses the other state and soft bit data is only determined for the less reliably sensed state. This…
PROGRAM DEPENDENT BIASING OF UNSELECTED SUB-BLOCKS
Granted: March 9, 2023
Application Number:
20230076245
An apparatus includes a control circuit configured to connect to first word lines of a first vertical sub-block and second word lines of a second vertical sub-block. The first vertical sub-block and the second vertical sub-block include memory cells connected in series in NAND strings, each NAND string including memory cells coupled to the first word lines in series with memory cells connected to the second word lines. The control circuit is configured to program or sense memory cells…
SUB-BLOCK PROGRAMMING MODE WITH MULTI-TIER BLOCK
Granted: March 2, 2023
Application Number:
20230069260
Apparatuses and techniques are described for programming a multi-tier block in which sub-blocks are arranged in respective tiers. When a program operation involves the source-side sub-block, the NAND strings are pre-charged from the source line. When a program operation involves the drain-side sub-block, the NAND strings are pre-charged from the bit line. When a program operation involves an interior sub-block, the NAND strings can be pre-charged from the bit line if all sub-blocks on…
MEMORY PROGRAMMING TECHNIQUES TO REDUCE POWER CONSUMPTION
Granted: March 2, 2023
Application Number:
20230066972
A memory device that includes a plurality of memory cells arranged in an array is provided. A control circuitry is configured to program a single bit of data in each memory cell of the plurality of memory cells. The control circuitry is further configured to program a first set of memory cells of the plurality of memory cells using a first programming operation that includes a single programming pulse and no verify pulse and program a second set of memory cells of the plurality of memory…
DETECTING BIT LINE OPEN CIRCUITS AND SHORT CIRCUITS IN MEMORY DEVICE WITH MEMORY DIE BONDED TO CONTROL DIE
Granted: March 2, 2023
Application Number:
20230061265
Apparatuses and techniques are presented for detecting bit line open circuits and short circuits in a memory device in which a memory die is inverted and bonded to a control die. In one approach, the control die comprises a set of bit lines which are connected to a set of bit lines of the memory die, and the set of bit lines of the control die comprise ground transistors, e.g., transistors connected to a ground node. Ground transistors of even-numbered bit lines may be commonly…
MODELLING AND PREDICTION OF VIRTUAL INLINE QUALITY CONTROL IN THE PRODUCTION OF MEMORY DEVICES
Granted: February 23, 2023
Application Number:
20230054342
To provide more test data during the manufacture of non-volatile memories and other integrated circuits, machine learning is used to generate virtual test values. Virtual test results are interpolated for one set of tests for devices on which the test is not performed based on correlations with other sets of tests. In one example, machine learning determines a correlation study between bad block values determined at die sort and photo-limited yield (PLY) values determined inline during…
CONTROLLING BIT LINE PRE-CHARGE VOLTAGE SEPARATELY FOR MULTI-LEVEL MEMORY CELLS AND SINGLE-LEVEL MEMORY CELLS TO REDUCE PEAK CURRENT CONSUMPTION
Granted: February 23, 2023
Application Number:
20230056891
Apparatuses and techniques are described for controlling a bit line pre-charge voltage in a program operation based on a number of bits per cell, with a goal to reduce peak current consumption. In one aspect, the ramp up of a bit line voltage to an inhibit level is optimized according to the number of bits per cell. The ramp up can involve increasing the bit line voltage from an initial level to a target voltage at a regulated rate, then increasing the bit line voltage from the target…
MODIFYING PROGRAM AND ERASE PARAMETERS FOR SINGLE-BIT MEMORY CELLS TO IMPROVE SINGLE-BIT/MULTI-BIT HYBRID RATIO
Granted: February 23, 2023
Application Number:
20230058038
Apparatuses and techniques are described for modifying program and erase parameters in a memory device in which memory cells can be operated in a single bit per cell (SLC) mode or a multiple bits per cell mode. In one approach, the stress on a set of memory cells in an SLC mode is reduced during programming and erasing when the number of program-erase cycles for the block in the SLC mode is below a threshold. For example, during programming, the program-verify voltage and program…
NON-VOLATILE MEMORY WITH EFFICIENT TESTING
Granted: February 23, 2023
Application Number:
20230058836
A non-volatile memory system performs an erase process followed by a program process to program blocks of memory cells. The erase process comprises erasing followed by erase verification. The system recovers data and records a strike for blocks that fail a read process. In response to a particular block having a strike, the system performs an odd/even compare process during the erase process for the particular blocks having the strike such that the odd/even compare process comprises…
NON-VOLATILE MEMORY WITH EFFICIENT TESTING DURING ERASE
Granted: February 23, 2023
Application Number:
20230059837
A non-volatile memory system erasing groups of connected memory cells separately performs erase verify for memory cells connected to even word lines to generate even results and erase verify for memory cells connected to odd word lines to generate odd results. The even results and the odd results are used to determine if the erase verify process indicates that the erasing has successful completed. In addition, for each group of connected memory cells, a last even result for the group is…
STRING BASED ERASE INHIBIT
Granted: February 16, 2023
Application Number:
20230049605
A non-volatile memory device, described herein, comprises: a plurality of memory strings and at least one control circuit in communication with the non-volatile memory cell array. The at least one control circuit is configured to perform, for the plurality of memory strings, one erase-verify iteration in an erase operation including determining whether at least one memory string of the plurality of memory strings passes an erase-verify test. The at least one control circuit is configured…
MEMORY DEVICE THAT IS OPTIMIZED FOR LOW POWER OPERATION
Granted: February 16, 2023
Application Number:
20230052121
A storage device that includes a non-volatile memory is provided. The non-volatile memory includes a control circuitry that is communicatively coupled to a memory block that includes memory cells arranged word lines. The control circuitry is configured to program the memory cells of a selected word line in a plurality of programming loops to store a single bit of data in each memory cell of the selected word line. The programming loops include programming operations and verify…
NON-VOLATILE MEMORY WITH SUB-BLOCK BASED SELF-BOOSTING SCHEME
Granted: February 16, 2023
Application Number:
20230050955
To help reduce program disturbs in non-selected NAND strings of a non-volatile memory, a sub-block based boosting scheme in introduced. For a three dimensional NAND memory structure, in which the memory cells above a joint region form an upper sub-block and memory cells below the joint region form a lower sub-block, dummy word lines in the joint region act as select gates to allow boosting at the sub-block level when the lower block is being programmed in a reverse order.
STRING BASED ERASE INHIBIT
Granted: February 16, 2023
Application Number:
20230049605
A non-volatile memory device, described herein, comprises: a plurality of memory strings and at least one control circuit in communication with the non-volatile memory cell array. The at least one control circuit is configured to perform, for the plurality of memory strings, one erase-verify iteration in an erase operation including determining whether at least one memory string of the plurality of memory strings passes an erase-verify test. The at least one control circuit is configured…
SEMI-CIRCLE DRAIN SIDE SELECT GATE MAINTENANCE BY SELECTIVE SEMI-CIRCLE DUMMY WORD LINE PROGRAM
Granted: February 16, 2023
Application Number:
20230046677
A memory apparatus and method of operation are provided. The apparatus includes apparatus including memory cells connected to word lines including at least one dummy word line and data word lines. The memory cells are arranged in strings and are configured to retain a threshold voltage. The apparatus also includes a control means coupled to the word lines and the strings and configured to identify ones of the memory cells connected to the at least one dummy word line with the threshold…
SEMI-CIRCLE DRAIN SIDE SELECT GATE MAINTENANCE BY SELECTIVE SEMI-CIRCLE DUMMY WORD LINE PROGRAM
Granted: February 16, 2023
Application Number:
20230046677
A memory apparatus and method of operation are provided. The apparatus includes apparatus including memory cells connected to word lines including at least one dummy word line and data word lines. The memory cells are arranged in strings and are configured to retain a threshold voltage. The apparatus also includes a control means coupled to the word lines and the strings and configured to identify ones of the memory cells connected to the at least one dummy word line with the threshold…
MEMORY DEVICE WITH IMPROVED ENDURANCE
Granted: February 16, 2023
Application Number:
20230053269
A storage device that includes a non-volatile memory with a control circuitry is provided. The control circuitry is communicatively coupled to a memory block that includes an array of memory cells. The control circuitry is configured to program one or more bits of data into the memory cells. The control circuitry is further configured to operate the non-volatile memory in a multi-bit per memory cell mode, monitor a usage metric while the non-volatile memory is operating in the multi-bit…
MEMORY DEVICE THAT IS OPTIMIZED FOR LOW POWER OPERATION
Granted: February 16, 2023
Application Number:
20230052121
A storage device that includes a non-volatile memory is provided. The non-volatile memory includes a control circuitry that is communicatively coupled to a memory block that includes memory cells arranged word lines. The control circuitry is configured to program the memory cells of a selected word line in a plurality of programming loops to store a single bit of data in each memory cell of the selected word line. The programming loops include programming operations and verify…
NON-VOLATILE MEMORY WITH SUB-BLOCK BASED SELF-BOOSTING SCHEME
Granted: February 16, 2023
Application Number:
20230050955
To help reduce program disturbs in non-selected NAND strings of a non-volatile memory, a sub-block based boosting scheme in introduced. For a three dimensional NAND memory structure, in which the memory cells above a joint region form an upper sub-block and memory cells below the joint region form a lower sub-block, dummy word lines in the joint region act as select gates to allow boosting at the sub-block level when the lower block is being programmed in a reverse order.
STRING BASED ERASE INHIBIT
Granted: February 16, 2023
Application Number:
20230049605
A non-volatile memory device, described herein, comprises: a plurality of memory strings and at least one control circuit in communication with the non-volatile memory cell array. The at least one control circuit is configured to perform, for the plurality of memory strings, one erase-verify iteration in an erase operation including determining whether at least one memory string of the plurality of memory strings passes an erase-verify test. The at least one control circuit is configured…
