MEMORY DEVICE WITH IMPROVED ENDURANCE
Granted: February 16, 2023
Application Number:
20230053269
A storage device that includes a non-volatile memory with a control circuitry is provided. The control circuitry is communicatively coupled to a memory block that includes an array of memory cells. The control circuitry is configured to program one or more bits of data into the memory cells. The control circuitry is further configured to operate the non-volatile memory in a multi-bit per memory cell mode, monitor a usage metric while the non-volatile memory is operating in the multi-bit…
MEMORY DEVICE THAT IS OPTIMIZED FOR LOW POWER OPERATION
Granted: February 16, 2023
Application Number:
20230052121
A storage device that includes a non-volatile memory is provided. The non-volatile memory includes a control circuitry that is communicatively coupled to a memory block that includes memory cells arranged word lines. The control circuitry is configured to program the memory cells of a selected word line in a plurality of programming loops to store a single bit of data in each memory cell of the selected word line. The programming loops include programming operations and verify…
NON-VOLATILE MEMORY WITH SUB-BLOCK BASED SELF-BOOSTING SCHEME
Granted: February 16, 2023
Application Number:
20230050955
To help reduce program disturbs in non-selected NAND strings of a non-volatile memory, a sub-block based boosting scheme in introduced. For a three dimensional NAND memory structure, in which the memory cells above a joint region form an upper sub-block and memory cells below the joint region form a lower sub-block, dummy word lines in the joint region act as select gates to allow boosting at the sub-block level when the lower block is being programmed in a reverse order.
SEMI-CIRCLE DRAIN SIDE SELECT GATE MAINTENANCE BY SELECTIVE SEMI-CIRCLE DUMMY WORD LINE PROGRAM
Granted: February 16, 2023
Application Number:
20230046677
A memory apparatus and method of operation are provided. The apparatus includes apparatus including memory cells connected to word lines including at least one dummy word line and data word lines. The memory cells are arranged in strings and are configured to retain a threshold voltage. The apparatus also includes a control means coupled to the word lines and the strings and configured to identify ones of the memory cells connected to the at least one dummy word line with the threshold…
SEMI-CIRCLE DRAIN SIDE SELECT GATE MAINTENANCE BY SELECTIVE SEMI-CIRCLE DUMMY WORD LINE PROGRAM
Granted: February 16, 2023
Application Number:
20230046677
A memory apparatus and method of operation are provided. The apparatus includes apparatus including memory cells connected to word lines including at least one dummy word line and data word lines. The memory cells are arranged in strings and are configured to retain a threshold voltage. The apparatus also includes a control means coupled to the word lines and the strings and configured to identify ones of the memory cells connected to the at least one dummy word line with the threshold…
RELIABILITY COMPENSATION FOR UNEVEN NAND BLOCK DEGRADATION
Granted: February 9, 2023
Application Number:
20230041476
Technology is provided for extending the useful life of a block of memory cells by changing an operating parameter in a physical region of the block that is more susceptible to wear than other regions. Changing the operating parameter in the physical region extends the life of that region, which extends the life of the block. The operating parameter may be, for example, a program voltage step size or a storage capacity of the memory cells. For example, using a smaller program voltage…
RELIABILITY COMPENSATION FOR UNEVEN NAND BLOCK DEGRADATION
Granted: February 9, 2023
Application Number:
20230041476
Technology is provided for extending the useful life of a block of memory cells by changing an operating parameter in a physical region of the block that is more susceptible to wear than other regions. Changing the operating parameter in the physical region extends the life of that region, which extends the life of the block. The operating parameter may be, for example, a program voltage step size or a storage capacity of the memory cells. For example, using a smaller program voltage…
NON-VOLATILE MEMORY WITH VARIABLE BITS PER MEMORY CELL
Granted: January 19, 2023
Application Number:
20230012977
In a three dimensional non-volatile memory structure that etches part of the top of the memory structure (including a portion of the select gates), data is stored on a majority (or all but one) of the word lines as x bits per memory cell while data is stored on a top edge word line that is closest to the etching with variable bits per memory cell. In one example embodiment that implements vertical NAND strings, memory cells connected to the top edge word line and that are on NAND strings…
NON-VOLATILE MEMORY WITH VARIABLE BITS PER MEMORY CELL
Granted: January 19, 2023
Application Number:
20230012977
In a three dimensional non-volatile memory structure that etches part of the top of the memory structure (including a portion of the select gates), data is stored on a majority (or all but one) of the word lines as x bits per memory cell while data is stored on a top edge word line that is closest to the etching with variable bits per memory cell. In one example embodiment that implements vertical NAND strings, memory cells connected to the top edge word line and that are on NAND strings…
POWER OFF RECOVERY IN CROSS-POINT MEMORY WITH THRESHOLD SWITCHING SELECTORS
Granted: January 5, 2023
Application Number:
20230005539
In a memory array with a cross-point structure, at each cross-point junction a programmable resistive memory element, such as an MRAM memory cell, is connected in series with a threshold switching selector, such as an ovonic threshold switch. The threshold switching selector switches to a conducting state when a voltage above a threshold voltage is applied. When powered down for extended periods, the threshold voltage can drift upward. If the drift is excessive, this can make the memory…
CONCURRENT MULTI-BIT ACCESS IN CROSS-POINT ARRAY
Granted: January 5, 2023
Application Number:
20230005530
Concurrent access of multiple memory cells in a cross-point memory array is disclosed. In one aspect, a forced current approach is used in which, while a select voltage is applied to a selected bit line, an access current is driven separately through each selected word line to concurrently drive the access current separately through each selected memory cell. Hence, multiple memory cells are concurrently accessed. In some aspects, the memory cells are accessed using a self-referenced…
VIRTUAL QUALITY CONTROL INTERPOLATION AND PROCESS FEEDBACK IN THE PRODUCTION OF MEMORY DEVICES
Granted: December 29, 2022
Application Number:
20220413036
To provide more test data during the manufacture of non-volatile memories and other integrated circuits, machine learning is used to generate virtual test values. Virtual test results are interpolated for one set of tests for devices on which the test is not performed based on correlations with other sets of tests. In one example, machine learning determines a correlation study between bad block values determined at die sort and photo-limited yield (PLY) values determined inline during…
VIRTUAL METROLOGY FOR FEATURE PROFILE PREDICTION IN THE PRODUCTION OF MEMORY DEVICES
Granted: December 29, 2022
Application Number:
20220415718
To provide more test data during the manufacture of non-volatile memories and other integrated circuits, machine learning is used to generate virtual test values. Virtual test results are interpolated for one set of tests for devices on which the test is not performed based on correlations with other sets of tests. In one example, machine learning determines a correlation study between bad block values determined at die sort and photo-limited yield (PLY) values determined inline during…
APPARATUS AND METHODS FOR SMART VERIFY WITH NEIGHBOR PLANE DISTURB DETECTION
Granted: December 29, 2022
Application Number:
20220415421
An apparatus is provided that includes a plurality of non-volatile memory cells and a control circuit coupled to the non-volatile memory cells. The control circuit is configured to perform a first program-verify iteration on a first set of non-volatile memory cells coupled to a first word line to determine a first starting program voltage that programs the first set of the non-volatile memory cells to a first programmed state, and program a second set of non-volatile memory cells coupled…
MEMORY PROGRAMMING WITH SELECTIVELY SKIPPED VERIFY PULSES FOR PERFORMANCE IMPROVEMENT
Granted: December 29, 2022
Application Number:
20220415417
The non-volatile memory includes a control circuitry that is communicatively coupled to an array of memory cells that are arranged in a plurality of word lines. The control circuitry is configured to program the memory cells of the plurality of word lines to a plurality of data states in a multi-pass programming operation. A later programming pass of the multi-pass programming operation includes a plurality of programming loops with incrementally increasing programming pulses. For at…
SYSTEMS AND METHODS FOR COMPENSATING FOR ERASE SPEED VARIATIONS DUE TO SEMI-CIRCLE SGD
Granted: December 29, 2022
Application Number:
20220415416
Non-volatile memory systems are disclosed. The memory systems include rows of memory holes FC-SGD and SC-SGD, the latter of which may be created by a SHE cutting operation. The SC-SGD include erase speeds slower than those of FC-SGD. In order to overcome the erase speed disparities, SC-SGD are programmed to a higher Vt as compared to FC-SGD. By programming SC-SGD to a higher Vt, the erase speed increases and matches the erase speed of FC-SGD. Further, different SC-SGDs are cut to…
?READ AFTER ERASE? METHOD FOR CATCHING SINGLE WORD LINE ?SLOW TO ERASE? SIGNATURE IN NON-VOLATILE MEMORY ST
Granted: December 29, 2022
Application Number:
20220415413
A method for detecting a “slow to erase” condition of a non-volatile memory structure, wherein the method comprises initiating an erase/verify memory operation with respect to the memory structure, wherein the erase/verify memory operation comprises applying an erase verify voltage according to an alternating word line scheme; following the erase/verify memory operation, determining if a first bit scan mode criteria is satisfied; and, if the first bit scan mode criteria is satisfied,…
STATE DEPENDENT VPVD VOLTAGES FOR MORE UNIFORM THRESHOLD VOLTAGE DISTRIBUTIONS IN A MEMORY DEVICE
Granted: December 29, 2022
Application Number:
20220415399
The storage device includes a non-volatile memory with control circuitry and an array of memory cells that are arranged in a plurality of word lines. The control circuitry is configured to program the memory cells in a plurality of programming loops which include applying a programming pulse to a selected word line to program at least one memory cell of the selected word line to a programmed data state. The programming loops also include simultaneously applying a verify pulse to the…
BLOCK CONFIGURATION FOR MEMORY DEVICE WITH SEPARATE SUB-BLOCKS
Granted: December 29, 2022
Application Number:
20220415398
A memory device is provided in which blocks of memory cells are divided into separate portions or sub-blocks with respective sets of word line switching transistors. The sub-blocks can be arranged on a substrate on opposite sides of a dividing line, where a separate set of bit lines is provided on each side of the dividing line. Each block has a row decoder which provides a common word line voltage signal to each sub-block of the block. However, each sub-block can have an independent set…
CONCURRENT MULTI-BIT ACCESS IN CROSS-POINT ARRAY
Granted: December 29, 2022
Application Number:
20220415387
Concurrent access of multiple memory cells in a cross-point memory array is disclosed. In one aspect, a forced current approach is used in which, while a select voltage is applied to a selected bit line, an access current is driven separately through each selected word line to concurrently drive the access current separately through each selected memory cell. Hence, multiple memory cells are concurrently accessed. In some aspects, the memory cells are accessed using a self-referenced…
