VIRTUAL QUALITY CONTROL INTERPOLATION AND PROCESS FEEDBACK IN THE PRODUCTION OF MEMORY DEVICES
Granted: December 29, 2022
Application Number:
20220413036
To provide more test data during the manufacture of non-volatile memories and other integrated circuits, machine learning is used to generate virtual test values. Virtual test results are interpolated for one set of tests for devices on which the test is not performed based on correlations with other sets of tests. In one example, machine learning determines a correlation study between bad block values determined at die sort and photo-limited yield (PLY) values determined inline during…
Sense Amplifier Mapping and Control Scheme for Non-Volatile Memory
Granted: December 22, 2022
Application Number:
20220406342
A data storage includes a memory array including a plurality of memory cells, and peripheral circuitry disposed underneath the memory array. The peripheral circuitry includes an M-tier sense amplifier (SA) circuit including X stacks of SA latches, wherein each SA latch is respectively coupled to a bit line of a memory cell of the plurality of memory cells; and an N-tier memory cache data (XDL) circuit including Y stacks of XDL latches, wherein M is less than N, and X is greater than Y.…
PROGRAMMING MEMORY CELLS WITH CONCURRENT STORAGE OF MULTI-LEVEL DATA AS SINGLE-LEVEL DATA FOR POWER LOSS PROTECTION
Granted: December 22, 2022
Application Number:
20220406398
Apparatuses and techniques are described for programming data in memory cells while concurrently storing backup data. Initial pages of multiple bit per cell data are encoded to obtain at least first and second pages of single bit per cell data. The initial pages of multiple bit per cell data are programmed into a primary set of memory cells, while concurrently the first and second pages of single bit per cell data are programmed into first and second backup sets of memory cells,…
REVERSE VT-STATE OPERATION AND OPTIMIZED BICS DEVICE STRUCTURE
Granted: December 22, 2022
Application Number:
20220406390
Systems and methods for improving the reliability of non-volatile memory by reducing the number of memory cell transistors that experience excessive hole injection are described. The excessive hole injection may occur when the threshold voltage for a memory cell transistor is being set below a particular negative threshold voltage. To reduce the number of memory cell transistors with threshold voltages less than the particular negative threshold voltage, the programmed data states of the…
STRING DEPENDENT SLC RELIABILITY COMPENSATION IN NON-VOLATILE MEMORY STRUCTURES
Granted: December 22, 2022
Application Number:
20220406389
A method for programming a memory block of a non-volatile memory structure, comprising determining whether a number of programming/erase cycles previously applied to the block exceeds a first programming/erase cycle threshold and, if the first threshold is exceeded, determining whether the number of programming/erase cycles previously applied to the block exceeds an extended programming/erase cycle threshold. Further, if the determination is made that the extended threshold is not…
Toggle Mode Frequency Optimization By Dynamic ODT Matching for Non-Volatile Memory
Granted: December 22, 2022
Application Number:
20220406387
A data storage system includes a plurality of memory dies and interface circuitry, including a receiver configured to receive pulses of a read clock signal; an I/O contact pad coupled to the receiver via a signal path of an interface channel; and on-die-termination (ODT) circuitry coupled to the I/O contact pad and the receiver. The ODT circuitry includes a plurality of resistor pairs, each including a pull-up resistor selectively coupled to the signal path via a first switch, and a…
DIGITAL TEMPERATURE COMPENSATION FILTERING
Granted: December 22, 2022
Application Number:
20220406383
Techniques disclosed herein cope with temperature effects in non-volatile memory systems. A control circuit is configured to sense a current temperature of the memory system and read, verify, program, and erase data in non-volatile memory cells by modifying one or more read/verify/program/erase parameters based on a temperature compensation value. The control circuit is further configured to read, verify, program, and erase data by accessing a historical temperature value stored in the…
WORD LINE ZONED ADAPTIVE INITIAL PROGRAM VOLTAGE FOR NON-VOLATILE MEMORY
Granted: December 22, 2022
Application Number:
20220406380
An apparatus is provided that includes a plurality of word lines that include a plurality of word line zones, a plurality of non-volatile memory cells coupled to the plurality of word lines, and a control circuit coupled to the non-volatile memory cells. The control circuit is configured to determine a corresponding initial program voltage for each of the word line zones. Each corresponding initial program voltage is determined based on a number of program erase cycles.
SYSTEMS AND METHODS FOR ADJUSTING THRESHOLD VOLTAGE DISTRIBUTION DUE TO SEMI-CIRCLE SGD
Granted: December 22, 2022
Application Number:
20220406378
The following disclosure is directed to mitigating issues related to semi-circle drain side select gate (SC-SGD) memory holes in memory structures. When a memory hole is cut, the channel and the charge trap layer of the memory hole cut. Further, the outer dielectric layer (used to shield the channel and the charge trap layer) is cut and partially removed. When the selected SC-SGD is selected for an operation (e.g., programming), the channel and the charge trap layer are exposed to…
Hetero-Plane Data Storage Structures For Non-Volatile Memory
Granted: December 22, 2022
Application Number:
20220406364
A flash memory die includes (i) a first subset of planes including blocks of flash memory cells connected to a first number of word line layers and a plurality of bit lines having a first length, (ii) a second subset of planes including blocks of flash memory cells connected to a second number of word line layers less than the first number of word line layers and a plurality of bit lines having a second length shorter than the first length, (iii) first peripheral circuitry implemented…
SEMI RECEIVER SIDE WRITE TRAINING FOR NON-VOLATILE MEMORY SYSTEM
Granted: December 22, 2022
Application Number:
20220405190
Technology is disclosed herein for semi receiver side write training in a non-volatile memory system. The transmitting device has delay taps that control the delay between a data strobe signal and data signals sent on the communication bus. The delay taps on the transmitting device are more precise that can typically be fabricated on the receiving device (e.g., NAND memory die). However, the receiving device performs the comparisons between test data and expected data, which alleviates…
PROGRAMMING MEMORY CELLS WITH CONCURRENT REDUNDANT STORAGE OF DATA FOR POWER LOSS PROTECTION
Granted: December 22, 2022
Application Number:
20220404989
Apparatuses and techniques are described for programming data in memory cells while concurrently storing backup data. One or more initial pages of data are programmed into both a primary block and a first backup block in a first program pass. A power loss then occurs which can corrupt the data or otherwise prevent reading of the one or more initial pages of data from the primary block. The one or more initial pages of data are read from the first backup block and used to perform a second…
COMPUTE IN MEMORY THREE-DIMENSIONAL NON-VOLATILE NOR MEMORY FOR NEURAL NETWORKS
Granted: December 15, 2022
Application Number:
20220398438
A non-volatile memory device for performing compute in memory operations for a neural network uses a three dimensional NOR architecture in which vertical NOR strings are formed of multiple memory cells connected in parallel between a source line and a bit line. Weights of the neural network are encoded as threshold voltages of the memory cells and activations are encoded as word line voltages applied to the memory cells of the NOR strings. The memory cells are operated in the…
NONVOLATILE MEMORY WITH LATCH SCRAMBLE
Granted: December 15, 2022
Application Number:
20220399072
An apparatus includes one or more control circuits configured to connect to a plurality of non-volatile memory cells arranged along word lines. The one or more control circuits are configured to receive a plurality of encoded portions of data to be programmed in non-volatile memory cells of a target word line, each encoded portion of data encoded according to an Error Correction Code (ECC) encoding scheme, and arrange the plurality of encoded portions of data in a plurality of rows of…
SMART ERASE VERIFY IN NON-VOLATILE MEMORY STRUCTURES
Granted: December 15, 2022
Application Number:
20220399065
A method for dynamically adjusting an erase voltage level to be applied in a subsequent erase cycle, comprising: in a current erase cycle, initiating a current erase/verify loop by applying an initial stored erase voltage level according to an erase sequence in which each successive erase/verify loop is incremented by a pre-determined voltage amount, storing an erase/verify loop count, and determining whether the current erase cycle is complete according to a pass criterion. If the erase…
SYSTEMS AND METHODS FOR COUNTING PROGRAM-ERASE CYCLES OF A CELL BLOCK IN A MEMORY SYSTEM
Granted: December 15, 2022
Application Number:
20220399064
This disclosure proposes a method to save P/E cycling information inside NAND by using 2-byte column in programmable selective devices (e.g., SGD). The proposed method is a one-way programming method, and does not perform an erase operation within the 2-byte column. The proposed methods described herein can reduce the burden of relying upon controller SRAM/DRAM. Additionally, by storing the P/E cycling information in NAND, the P/E cycling is not lost due to a power loss event. At least…
Fast Sensing Scheme With Amplified Sensing and Clock Modulation
Granted: December 15, 2022
Application Number:
20220399062
A method of verifying the programming of a plurality of memory cells in a data storage system includes performing a setup operation including settling of bit lines associated with the subset of memory cells; performing a sensing operation including subjecting the settled bit lines to a verify voltage signal; and performing first and second latching operations identifying memory cells of the subset of memory cells having threshold voltages that meet first and second verify reference…
COUNTERMEASURE MODES TO ADDRESS NEIGHBOR PLANE DISTURB CONDITION IN NON-VOLATILE MEMORY STRUCTURES
Granted: December 15, 2022
Application Number:
20220399061
Countermeasure method for programming a non-defective plane of a non-volatile memory experiencing a neighbor plane disturb, comprising, once a first plane is determined to have completed programming of a current state but where not all planes have completed the programming, a loop count is incremented and a determination is made as to whether the loop count exceeds a threshold. If so, programming of the incomplete plane(s) is ceased and programming of the completed plane(s) is resumed by…
MEMORY APPARATUS AND METHOD OF OPERATION USING DYNAMIC MAX PROGRAM LOOP
Granted: December 15, 2022
Application Number:
20220399058
A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and arranged in strings and configured to retain a threshold voltage corresponding to memory states. A control circuit is configured to program the memory cells to reach one of a plurality of verify levels each corresponding the memory states using a series of voltage pulses applied to the word lines during a program operation. The control circuit determines an…
COMPUTE IN MEMORY THREE-DIMENSIONAL NON-VOLATILE NAND MEMORY FOR NEURAL NETWORKS WITH WEIGHT AND INPUT LEVEL EXPANSIONS
Granted: December 15, 2022
Application Number:
20220398439
A non-volatile memory device for performing compute in memory operations for a neural network uses a three dimensional NAND architecture. Multi-bit weight values are stored encoded as sets of threshold voltages for sets of memory cells. A weight value is stored in multiple memory cells on the same word line and connected between a bit line and a source line, each of the memory cells programmed to one of multiple threshold voltages. When multiplying an input value with the weight value,…
