NON-VOLATILE MEMORY WITH OPTIMIZED ERASE VERIFY SEQUENCE
Granted: February 8, 2024
Application Number:
20240047000
An erase process for a group of non-volatile memory cells comprises applying doses of erasing to the group and performing erase verify between pairs of successive doses of erasing. The time needed to complete the erase process can be reduced by optimizing the order of performing erase verify. For example, erase verify can be performed by separately performing erase verify for multiple portions of the group in order from previously determined slowest erasing portion of the group to…
NON-VOLATILE MEMORY WITH NARROW AND SHALLOW ERASE
Granted: February 8, 2024
Application Number:
20240046996
In a non-volatile memory, to achieve a shallow and tight erased threshold voltage distribution, a process is performed that includes erasing a group of non-volatile memory cells, identifying a first set of the bit lines that are connected to non-volatile memory cells of the group that are erased past a lower limit for erased non-volatile memory cells and identifying a second set of the bit lines that are connected to non-volatile memory cells of the group that are not erased past the…
NON-VOLATILE MEMORY WITH OPTIMIZED ERASE VERIFY SEQUENCE
Granted: February 8, 2024
Application Number:
20240047000
An erase process for a group of non-volatile memory cells comprises applying doses of erasing to the group and performing erase verify between pairs of successive doses of erasing. The time needed to complete the erase process can be reduced by optimizing the order of performing erase verify. For example, erase verify can be performed by separately performing erase verify for multiple portions of the group in order from previously determined slowest erasing portion of the group to…
NON-VOLATILE MEMORY WITH NARROW AND SHALLOW ERASE
Granted: February 8, 2024
Application Number:
20240046996
In a non-volatile memory, to achieve a shallow and tight erased threshold voltage distribution, a process is performed that includes erasing a group of non-volatile memory cells, identifying a first set of the bit lines that are connected to non-volatile memory cells of the group that are erased past a lower limit for erased non-volatile memory cells and identifying a second set of the bit lines that are connected to non-volatile memory cells of the group that are not erased past the…
EARLY DETECTION OF PROGRAMMING FAILURE FOR NON-VOLATILE MEMORY
Granted: February 1, 2024
Application Number:
20240038315
An apparatus is provided that includes a block including a word line coupled to a plurality of memory cells, and a control circuit coupled to the word line. The control circuit is configured to program the plurality of memory cells by applying program pulses to the word line in a plurality of program loops, determining a first count of a number of the program loops used to complete programming a first subset of the plurality of memory cells to a first programmed state, first comparing…
NON-VOLATILE MEMORY WITH OPTIMIZED OPERATION SEQUENCE
Granted: February 1, 2024
Application Number:
20240036740
A non-volatile memory system separately performs a memory operation for multiple sub-blocks of a block in order from previously determined slowest sub-block of the block to a previously determined faster sub-block of the block. As a slower sub-block is more likely to fail, this order of is more likely to identify a failure earlier in the process thereby saving time and reducing potential for a disturb. In some embodiments, the proposed order of operation can be used in conjunction with a…
NON-VOLATILE MEMORY WITH OPTIMIZED OPERATION SEQUENCE
Granted: February 1, 2024
Application Number:
20240036740
A non-volatile memory system separately performs a memory operation for multiple sub-blocks of a block in order from previously determined slowest sub-block of the block to a previously determined faster sub-block of the block. As a slower sub-block is more likely to fail, this order of is more likely to identify a failure earlier in the process thereby saving time and reducing potential for a disturb. In some embodiments, the proposed order of operation can be used in conjunction with a…
EARLY DETECTION OF PROGRAMMING FAILURE FOR NON-VOLATILE MEMORY
Granted: February 1, 2024
Application Number:
20240038315
An apparatus is provided that includes a block including a word line coupled to a plurality of memory cells, and a control circuit coupled to the word line. The control circuit is configured to program the plurality of memory cells by applying program pulses to the word line in a plurality of program loops, determining a first count of a number of the program loops used to complete programming a first subset of the plurality of memory cells to a first programmed state, first comparing…
NON-VOLATILE MEMORY WITH ONE SIDED PHASED RAMP DOWN AFTER PROGRAM-VERIFY
Granted: January 25, 2024
Application Number:
20240029806
In a non-volatile memory system that performs programming of selected memory cells (in coordination with pre-charging and boosting of channels for unselected memory cells) and program-verify to determine whether the programming was successful, the system transitions from program-verify to the next dose of programming by concurrently lowering a voltage applied to a selected word line and voltages applied to word lines on a first side of the selected word line at the conclusion of…
ADAPTIVE FAIL BITS THRESHOLD NUMBER FOR ERASING NON-VOLATILE MEMORY
Granted: January 25, 2024
Application Number:
20240029804
An apparatus is provided that includes a block of memory cells and a control circuit coupled to the block of memory cells. The control circuit is configured to perform an erase operation on the block of memory cells by determining a first count of a number of times that the block of memory cells previously has been programmed and erased, determining a threshold number based on the first count, and determining whether the erase operation passed or failed based on the threshold number.
MEMORY DIE HAVING A UNIQUE STORAGE CAPACITY
Granted: January 25, 2024
Application Number:
20240029789
The memory die that includes a plurality of memory blocks. Each memory block includes a plurality of memory cells that are configured to store three bits of data in each memory cell when the memory die is in a TLC operating mode. The memory die has a non-binary data capacity, which is a multiple of 683 Gb, when the memory die is operating in the TLC operating mode.
NON-VOLATILE MEMORY WITH ONE SIDED PHASED RAMP DOWN AFTER PROGRAM-VERIFY
Granted: January 25, 2024
Application Number:
20240029806
In a non-volatile memory system that performs programming of selected memory cells (in coordination with pre-charging and boosting of channels for unselected memory cells) and program-verify to determine whether the programming was successful, the system transitions from program-verify to the next dose of programming by concurrently lowering a voltage applied to a selected word line and voltages applied to word lines on a first side of the selected word line at the conclusion of…
ADAPTIVE FAIL BITS THRESHOLD NUMBER FOR ERASING NON-VOLATILE MEMORY
Granted: January 25, 2024
Application Number:
20240029804
An apparatus is provided that includes a block of memory cells and a control circuit coupled to the block of memory cells. The control circuit is configured to perform an erase operation on the block of memory cells by determining a first count of a number of times that the block of memory cells previously has been programmed and erased, determining a threshold number based on the first count, and determining whether the erase operation passed or failed based on the threshold number.
MEMORY DIE HAVING A UNIQUE STORAGE CAPACITY
Granted: January 25, 2024
Application Number:
20240029789
The memory die that includes a plurality of memory blocks. Each memory block includes a plurality of memory cells that are configured to store three bits of data in each memory cell when the memory die is in a TLC operating mode. The memory die has a non-binary data capacity, which is a multiple of 683 Gb, when the memory die is operating in the TLC operating mode.
NON-VOLATILE MEMORY WITH SUSPENSION PERIOD DURING PROGRAMMING
Granted: January 4, 2024
Application Number:
20240006002
To remedy short term data retention issues, a system creates a gate to channel voltage differential for non-volatile memory cells between programming and verifying in order to accelerate the effects of the short term data retention issue. That is, the gate to channel voltage differential will accelerate the migrating of electrons out of shallow traps. In some embodiments, the gate to channel voltage differential comprises a higher voltage at the channel in comparison to the gate. In some…
NON-VOLATILE MEMORY WITH SHORT PREVENTION
Granted: December 28, 2023
Application Number:
20230420055
To prevent loss of data due to a word line to memory hole short (or another defect), it is proposed to perform an erase process for a plurality of memory cells, detect that a subset of the plurality of memory cells are slow to erase, and prevent successfully programming for at least some of the memory cells that are slow to erase. This technique uses the erase process to predict future word line to memory hole shorts and prevent programming of memory cells predicted to have a future word…
TECHNIQUES FOR CHECKING VULNERABILITY TO CROSS-TEMPERATURE READ ERRORS IN A MEMORY DEVICE
Granted: December 28, 2023
Application Number:
20230420053
The memory device includes a memory block with an array of memory cells. The memory device also includes control circuitry that is in communication with the memory cells. The control circuitry is configured to program a group of the memory cells in a programming operation that does not include verify to obtain a natural threshold voltage (nVt) distribution, calculate an nVt width of the nVt distribution, compare the nVt width to a threshold, and identify the memory block as being…
RELIABILITY IMPROVEMENT THROUGH DELAY BETWEEN MULTI-STAGE PROGRAMMING STEPS IN NON-VOLATILE MEMORY STRUCTURES
Granted: December 28, 2023
Application Number:
20230420051
A method for multi-stage programming of a non-volatile memory structure, wherein the method comprises: (1) initiating a programming operation with respect to a memory block, (2) applying a programming algorithm to the memory block, wherein the programming algorithm comprises at least a first programming stage and a second programming stage, and (3) between the first programming stage and the second programming stage, applying a time delay according to a pre-determined amount of time.…
MEMORY DEVICE WITH UNIQUE READ AND/OR PROGRAMMING PARAMETERS
Granted: December 28, 2023
Application Number:
20230420042
The memory device includes a plurality of memory blocks that can individually operate in either a multi-bit per memory cell mode or a single-bit per memory cell mode. Certain voltage parameters during programming and reading are shared between these two operating modes, and certain voltage parameters are unique to each operating mode. One unique voltage parameter is a pass voltage VREADK that is applied to word lines adjacent a selected word line being read. Another unique voltage…
DIE BY DIE TRIMMING OF DRAIN-SIDE SELECT GATE THRESHOLD VOLTAGE TO REDUCE CUMULATIVE READ DISTURB
Granted: December 21, 2023
Application Number:
20230410912
A memory apparatus and method of operation are provided. The apparatus includes drain-side select gate transistors for coupling to a drain-side of each of a plurality of memory holes of memory cells and configured to retain a transistor threshold voltage. The memory apparatus also includes a control means coupled to the drain-side select gate transistor of each of the plurality of memory holes. The control means is configured to select the transistor threshold voltage of the drain-side…
