NON-VOLATILE MEMORY WITH ERASE DEPTH DETECTION AND ADAPTIVE ADJUSTMENT TO PROGRAMMING
Granted: June 27, 2024
Application Number:
20240212768
A non-volatile memory system detects an indication of erase depth of a population of memory cells and adjusts the programming process for the memory cells based on the detected erase depth.
MULTI-STAGE PROGRAMMING TECHNIQUES WITH THREE STATES PER MEMORY CELL PARITY
Granted: June 27, 2024
Application Number:
20240212767
The memory device includes a memory block with an array of memory cells arranged word lines. The memory device also includes control circuitry that is configured to program final data into a selected word line in a multi-pass programming operation that includes a first pass and a second pass. In the first pass, the control circuitry is configured to program the memory cells of the selected word line to foggy data and program parity data in the memory device. The parity data includes…
APPARATUS AND METHOD FOR DETECTING NEIGHBOR PLANE ERASE FAILURES
Granted: June 27, 2024
Application Number:
20240212764
An apparatus is provided that includes a control circuit coupled to a plurality of non-volatile memory cells disposed in a plurality of planes. The control circuit is configured to concurrently erase a block of memory cells in each of the plurality of planes, determine that the concurrent erase failed, disconnect a first one of the planes from the plurality of planes to form first remaining planes, and concurrently erase a block of memory cells in each of the first remaining planes.
X-DIRECTION DIVIDED SUB-BLOCK MODE IN NAND
Granted: June 27, 2024
Application Number:
20240212755
A memory system is described having an x-direction (bit line direction) divided sub-block mode. Each block is divided in a y-direction and in the x-direction into a number of groups of contiguous NAND strings that are referred to as XY sub-blocks. The memory system performs a memory operation in parallel in multiple XY sub-blocks in a block while inhibiting the memory operation in the other XY sub-blocks in the block. Each XY sub-block for which the memory operation is performed has its…
WORD LINE-DEPENDENT WORD LINE AND CHANNEL READ SETUP TIME IN FIRST READ STATE OF NON-VOLATILE MEMORY
Granted: June 27, 2024
Application Number:
20240212737
A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and disposed in memory holes each comprising a channel. The memory cells retain a threshold voltage and are operable in one of a first read condition in which a word line voltage of the word lines is discharged and a second read condition in which the word line voltage of the word lines is coupled up to a residual voltage level. A control means is configured to apply a…
TEMPERATURE COMPENSATION FOR PRE-CHARGE SPIKE IN MULTI-PASS PROGRAMMING
Granted: June 20, 2024
Application Number:
20240201882
The present disclosure is related to a programming technique for a memory device that includes a plurality of memory cells arranged in a plurality of word lines. An operating temperature of the memory device is determined. A spike pre-charge voltage is selected based on the operating temperature of the memory device. A first word line and a second word line are programmed in a first programming pass of a multi-pass programming operation. After the first programming pass is completed on…
APPARATUS AND METHODS FOR SMART VERIFY WITH ADAPTIVE VOLTAGE OFFSET
Granted: June 20, 2024
Application Number:
20240203512
An apparatus is provided that includes a control circuit coupled to a plurality of non-volatile memory cells. The control circuit is configured to perform a program-verify iteration on a first set of the non-volatile memory cells in a plurality of program loops, determine that the first set of the non-volatile memory cells passes verification to a particular programmed state in a first number of program loops, determine a first voltage based on the first number of program loops, add an…
CHANNEL PRE-CHARGE PROCESS IN A MEMORY DEVICE
Granted: June 20, 2024
Application Number:
20240203511
The memory device includes a memory block with memory cells arranged in word lines that are divided into sub-blocks. Control circuitry is configured to program each of the word lines of a selected sub-blocks in a plurality of program loops. During at least one program loop, the control circuitry applies a programming pulse to a selected word line. The control circuitry is also configured to simultaneously apply a verify voltage to the selected word line and a pass voltage to unselected…
NON-VOLATILE MEMORY WITH HOLE PRE-CHARGE AND ISOLATED SIGNAL LINES
Granted: June 20, 2024
Application Number:
20240203506
A non-volatile memory system programs memory cells from an erased threshold voltage distribution to programmed threshold voltage distributions by performing hole pre-charging of channels of unselected NAND strings in a selected block of a selected plane including applying a source voltage to a selected signal line of a plurality of signal lines that are isolated from each other. The selected signal line is positioned between the selected block and an unselected block and is connected to…
IMPLEMENTATION OF DEEP NEURAL NETWORKS FOR TESTING AND QUALITY CONTROL IN THE PRODUCTION OF MEMORY DEVICES
Granted: June 20, 2024
Application Number:
20240202425
Techniques are presented for the application of neural networks to the fabrication of integrated circuits and electronic devices, where example are given for the fabrication of non-volatile memory circuits and the mounting of circuit components on the printed circuit board of a solid state drive (SSD). The techniques include the generation of high precision masks suitable for analyzing electron microscope images of feature of integrated circuits and of handling the training of the neural…
MEMORY PROGRAM-VERIFY WITH ADAPTIVE SENSE TIME BASED ON DISTANCE FROM A WORD LINE DRIVER
Granted: June 13, 2024
Application Number:
20240194278
Technology is disclosed herein for a memory system that includes one or more control circuits configured to connect to a three-dimensional memory structure that includes word lines, with each word line connected to a word line driver at one end. The one or more control circuits are configured to, in a program verify operation, sense memory cells of a first region of a selected word line for a first sense time and sense memory cells of a second region of the selected word line for a…
MEMORY PROGRAM-VERIFY WITH ADAPTIVE SENSE TIME BASED ON ROW LOCATION
Granted: June 13, 2024
Application Number:
20240194277
Technology is disclosed herein for a memory system that includes control circuits that are configured to connect to a three-dimensional memory structure. The memory structure includes NAND strings arranged in a plurality of rows, a plurality of bit lines connected to the NAND strings and a plurality of word lines, each word line coupled to the plurality of rows of NAND strings. The control circuits are configured to, in a program-verify operation, sense memory cells of a first row of…
MULTI-TIER SUB-BLOCK MODE OPERATION
Granted: June 13, 2024
Application Number:
20240192873
A storage device is disclosed herein. The storage device comprises a non-volatile memory, where the non-volatile memory includes a block of 3N wordlines partitioned into a plurality of sub-blocks. The plurality of sub-blocks include an upper sub-block of a first subset of the block of 3N wordlines, a lower sub-block of a second subset of the block of 3N wordlines, and a middle sub-block of a third subset of the block of 3N wordlines. Further, the storage device comprises control…
BITLINE TIMING-BASED MULTI-STATE PROGRAMMING IN NON-VOLATILE MEMORY STRUCTURES
Granted: June 6, 2024
Application Number:
20240185914
A method for multi-state programming of a non-volatile memory structure, comprising: (1) initiating a programming operation with respect to multiple program states, (2) applying, to all selected word lines of the memory structure, a programming voltage bias (VPGM) level pre-determined to be suitable for programming a highest program state of the multiple program states, wherein the programming voltage bias level is applied according to a given program pulse width, and (3) with respect to…
FAST SELF-REFERENCED READ OF PROGRAMMABLE RESISTANCE MEMORY CELLS
Granted: June 6, 2024
Application Number:
20240184478
Technology is disclosed herein for reading programmable resistance memory cells. A first (faster) self-referenced read (SRR) of a group of memory cells is performed and if successful the read is complete. However, if the first SRR fails then a second (slower or nominal) SRR is performed. The bit error rate (BER) of the second SRR may be significantly lower than the BER of the first SRR. However, the BER of the first SRR may be low enough such that most of the time the first SRR is…
HYBRID TRIPLE LEVEL CELL PROGRAMMING ALGORITHM FOR ON PITCH SCALING IN BIT COST SCALABLE MEMORY APPARATUSES AND SUB-BLOCK MODE
Granted: June 6, 2024
Application Number:
20240184468
A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to one of a plurality of word lines and disposed in memory holes. The memory cells are configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is coupled to the plurality of word lines and the memory holes and is configured to identify at least one grouping of the memory cells to be programmed with a multi-pass programming…
ADAPTIVE ERASE VOLTAGES FOR NON-VOLATILE MEMORY
Granted: May 30, 2024
Application Number:
20240177788
An apparatus is provided that includes a block of memory cells, and a control circuit coupled to the block of memory cells. The control circuit is configured to perform an erase operation on the block of memory cells by determining a count of a number of times that the block of memory cells previously has been programmed and erased, determining an erase voltage based on the count, and applying an erase pulse having the erase voltage to the block of memory cells.
NON-VOLATILE MEMORY WITH ADAPTIVE DUMMY WORD LINE BIAS
Granted: May 30, 2024
Application Number:
20240177778
A non-volatile storage apparatus includes non-volatile memory cells, word lines connected to the non-volatile memory cells, and a control circuit connected to the word lines and the memory cells. The word lines include data word lines and dummy word lines. Memory cells connected to data word lines are configured to store host data. Memory cells connected to dummy word lines do not store host data. The control circuit is configured to erase, program and read the memory cells. Errors from…
EARLY PROGRAM TERMINATION WITH ADAPTIVE TEMPERATURE COMPENSATION
Granted: May 23, 2024
Application Number:
20240168661
An apparatus is provided that includes a control circuit coupled to a plurality of non-volatile memory cells. The control circuit is configured to perform a program-verify iteration on a first set of the non-volatile memory cells and a second set of the non-volatile memory cells in a plurality of program loops, determine that at least one of the first set of the non-volatile memory cells and the second set of the non-volatile memory cells verification to a programmed state in a first…
VERA DETECTION METHOD TO CATCH ERASE FAIL
Granted: May 16, 2024
Application Number:
20240161858
Technology is disclosed herein for quickly determining which erase block is bad if there is a failure in parallel erasing a set of erase blocks. The erase blocks may be tested individually in response to a fail of the parallel multi-block erase. A voltage generator ramps up the erase voltage from a steady state magnitude towards a target magnitude. The magnitude of the erase voltage is measured at a pre-determined time. If there is a defect then the erase voltage may fail to be above a…
