RELIABILITY IMPROVEMENT THROUGH DELAY BETWEEN MULTI-STAGE PROGRAMMING STEPS IN NON-VOLATILE MEMORY STRUCTURES
Granted: December 28, 2023
Application Number:
20230420051
A method for multi-stage programming of a non-volatile memory structure, wherein the method comprises: (1) initiating a programming operation with respect to a memory block, (2) applying a programming algorithm to the memory block, wherein the programming algorithm comprises at least a first programming stage and a second programming stage, and (3) between the first programming stage and the second programming stage, applying a time delay according to a pre-determined amount of time.…
MEMORY DEVICE WITH UNIQUE READ AND/OR PROGRAMMING PARAMETERS
Granted: December 28, 2023
Application Number:
20230420042
The memory device includes a plurality of memory blocks that can individually operate in either a multi-bit per memory cell mode or a single-bit per memory cell mode. Certain voltage parameters during programming and reading are shared between these two operating modes, and certain voltage parameters are unique to each operating mode. One unique voltage parameter is a pass voltage VREADK that is applied to word lines adjacent a selected word line being read. Another unique voltage…
TEMPERATURE-DEPENDENT WORD LINE VOLTAGE AND DISCHARGE RATE FOR REFRESH READ OF NON-VOLATILE MEMORY
Granted: December 21, 2023
Application Number:
20230410901
A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to one of a plurality of word lines. The memory cells are disposed in strings and configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is coupled to the plurality of word lines and the strings and is configured to apply a read voltage to a selected ones of the plurality of word lines during a read operation and ramp down to a…
HYBRID PRECHARGE SELECT SCHEME TO SAVE PROGRAM ICC
Granted: December 21, 2023
Application Number:
20230410923
A storage device comprises: a non-volatile memory including control circuitry and an array of memory cells formed using a set of word lines and a set of bit lines. A controller, coupled to the non-volatile memory, configured to: during a program loop for programming a set of states, select a first bitline biasing mode that dictates a scheme for biasing a first set of bitlines and apply the first bitline biasing mode before verifying the set of states. The controller further configured to…
REFRESH FREQUENCY-DEPENDENT SYSTEM-LEVEL TRIMMING OF VERIFY LEVEL OFFSETS FOR NON-VOLATILE MEMORY
Granted: December 21, 2023
Application Number:
20230410922
A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to word lines. The memory cells are disposed in strings and configured to retain a threshold voltage corresponding to data states. A control means is configured to apply verification pulses of program verify voltages each associated with one of the data states to selected ones of the word lines to determine whether the memory cells connected thereto have the threshold voltage above…
THREE-BIT-PER-CELL PROGRAMMING USING A FOUR-BIT-PER-CELL PROGRAMMING ALGORITHM
Granted: December 21, 2023
Application Number:
20230410921
An apparatus is provided that includes a plurality of memory cells, logic circuits coupled to the memory cells and configured to store 4-bit data in each of the memory cells, and a control circuit coupled to the memory cells and the logic circuits. The control circuit configured to cause the logic circuits to store 3-bit data in each of the memory cells.
READ PASS VOLTAGE DEPENDENT RECOVERY VOLTAGE SETTING BETWEEN PROGRAM AND PROGRAM VERIFY
Granted: December 21, 2023
Application Number:
20230410920
A memory apparatus and method of operation are provided. The apparatus includes memory cells connected word lines. The memory cells are disposed in strings and configured to retain a threshold voltage. A control means is configured to apply a program voltage to selected ones of the word lines while applying pass voltages to unselected ones of the word lines and ramp down both the selected ones of the plurality of word lines and the unselected ones of the word lines to a recovery voltage…
DIE BY DIE TRIMMING OF DRAIN-SIDE SELECT GATE THRESHOLD VOLTAGE TO REDUCE CUMULATIVE READ DISTURB
Granted: December 21, 2023
Application Number:
20230410912
A memory apparatus and method of operation are provided. The apparatus includes drain-side select gate transistors for coupling to a drain-side of each of a plurality of memory holes of memory cells and configured to retain a transistor threshold voltage. The memory apparatus also includes a control means coupled to the drain-side select gate transistor of each of the plurality of memory holes. The control means is configured to select the transistor threshold voltage of the drain-side…
BALANCING PEAK POWER WITH PROGRAMMING SPEED IN NON-VOLATILE MEMORY
Granted: December 21, 2023
Application Number:
20230410911
Technology is disclosed herein for a memory system that balances peak Icc with programming speed. A memory system applies voltages to respective word lines during a verify operation that balances peak Icc with programming speed. The voltages for which the ramp rate is controlled include a read pass voltage applied to unselected word lines and a spike voltage applied to the selected word line at the beginning of the verify. The ramp rate of the voltages is slow enough to keep the peak Icc…
DUMMY CELL RESISTANCE TUNING IN NAND STRINGS
Granted: December 21, 2023
Application Number:
20230410906
An apparatus includes a control circuit configured to connect to memory cells connected in series in NAND strings. Each NAND string includes a plurality of data memory cells coupled to a plurality of data word lines in series with a plurality of dummy memory cells connected to a plurality of dummy word lines. The control circuit configured to apply a first dummy word line voltage to one or more dummy word lines of the plurality of dummy word lines in a verify step of a program operation…
SECURE WEAR LEVELLING OF NON-VOLATILE MEMORY BASED ON GALOIS FIELD CIRCUIT
Granted: December 21, 2023
Application Number:
20230410867
Wear levelling techniques based on use of a Galois field for the logical to physical translation of data addresses for a non-volatile memory, such as an MRAM-based memory, are presented. This not only provides a wear levelling technique to extend memory life, but also adds an additional layer of security to the stored memory data. More specifically, the following presents embodiments for secure wear levelling based on a Galois field having an order based on the size of the memory. To…
STATE LOOK AHEAD QUICK PASS WRITE ALGORITHM TO TIGHTEN ONGOING NATURAL THRESHOLD VOLTAGE OF UPCOMING STATES FOR PROGRAM TIME REDUCTION
Granted: December 14, 2023
Application Number:
20230402110
A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines. The memory cells are disposed in strings and are configured to retain a threshold voltage corresponding to data states. A control means is configured to apply verification pulses of program verify voltages each associated with one of the data states to selected ones of the word lines to determine whether the memory cells connected thereto have the threshold voltage above…
HIGH SPEED TOGGLE MODE TRANSMITTER WITH CAPACITIVE BOOSTING
Granted: December 14, 2023
Application Number:
20230402107
An interface circuit that can operate in toggle mode at data high transfer rates while reducing the self-induced noise is presented. The high speed toggle mode interface supplies a data signal to a data line or other transfer line by a driver circuit. The driver circuit includes a pair of series connected transistors connected between a high supply level and a low supply level, where the data line is supplied from a node between the two transistors. A resistor is connected between one or…
READ TECHNIQUES TO REDUCE READ ERRORS IN A MEMORY DEVICE
Granted: December 14, 2023
Application Number:
20230402105
The memory device includes a memory block with a plurality of memory cells, which are programmed to multiple bits per memory cell, arranged in a plurality of word lines. Control circuitry is provided and is configured to read the memory cells of a selected word line. The control circuitry separates the memory cells of the selected word line into a first group of memory cells, which are located on a side of the word line are near a voltage driver, and a second group of memory cells, which…
ARRAY DEPENDENT VOLTAGE COMPENSATION IN A MEMORY DEVICE
Granted: December 14, 2023
Application Number:
20230402099
The memory device that includes a die with a CMOS wafer with programming and erasing circuitry. The die also includes a plurality of array wafers coupled with and in electrical communication with the CMOS wafer and having different programming and erasing efficiencies. Each of the array wafers includes memory blocks with memory cells. The control circuitry of the CMOS wafer is configured to output at least one of different initial programming voltages and unique erase voltages to the…
NON-VOLATILE MEMORY WITH TUNING OF ERASE PROCESS
Granted: December 7, 2023
Application Number:
20230395157
In order to achieve tight and uniform erased threshold voltage distributions in a non-volatile memory system that includes non-volatile memory cells arranged in blocks that have multiple sub-blocks and has an erase process using gate induced drain leakage (GIDL) to generate charge carriers that change threshold voltage of the memory cells, the magnitude of the GIDL is adjusted separately for the sub-blocks.
CROSS-POINT ARRAY REFRESH SCHEME
Granted: November 30, 2023
Application Number:
20230386543
Technology is disclosed herein for refreshing threshold switching selectors in programmable resistance memory cells in cross-point memory arrays. The Vt of the threshold switching selector may drift over time. The memory system resets the Vt of the threshold switching selectors with a selector refresh operation and uses a separate data refresh operation to refresh data in programmable resistance memory elements. The data refresh operation itself may also refresh the selector. However,…
TEMPERATURE DEPENDENT PROGRAMMING TECHNIQUES IN A MEMORY DEVICE
Granted: November 30, 2023
Application Number:
20230386586
The memory device that includes a plurality of memory cells that are arranged in a plurality of word lines. A controller is in electrical communication with the plurality of memory cells. During programming, the controller detects a temperature of the memory device. The controller then programs the memory cells of a selected word line of the plurality of word lines in a plurality of program loops until programming is completed or until the plurality of program loops is greater than a…
LOW POWER MULTI-LEVEL CELL (MLC) PROGRAMMING IN NON-VOLATILE MEMORY STRUCTURES
Granted: November 30, 2023
Application Number:
20230386569
A method for programming a memory array of a non-volatile memory structure, the memory comprising a population of MLC NAND-type memory cells, wherein the method comprises applying: (1) an inhibit condition to one or more bit lines of the memory array, and (2) a zero voltage condition to one or more bit lines of the memory array such that less than half of the adjacent bit lines of the memory array experience a voltage swing between the inhibit condition and the zero voltage condition.
HIGH SPEED MULTI-LEVEL CELL (MLC) PROGRAMMING IN NON-VOLATILE MEMORY STRUCTURES
Granted: November 30, 2023
Application Number:
20230386568
A method for programming a memory array of a non-volatile memory structure, wherein the memory array comprises a population of MLC NAND-type memory cells, and the method comprises: (1) in a first program pulse, programming selected memory cells according to a first programmable state and a second programmable state, and (2) in a second program pulse, programming the selected memory cells according to a third programmable state.
