Data storage device and method for memory-die-state-aware host command submission
Granted: August 20, 2024
Patent Number:
12067289
A data storage device and method for memory-die-state-aware host command submission are provided. In one embodiment, a data storage device comprises a memory comprising a plurality of memory dies and a controller. The controller is configured to receive a query from a host for a status of a memory die that will be accessed by a command; determine the status of the memory die; and respond to the query by providing the status of the memory die to the host. Other embodiments are possible,…
Data storage device and method for dynamic prediction of random read with low memory consumption
Granted: August 20, 2024
Patent Number:
12067268
A data storage device and method for dynamic prediction of random read with low memory consumption are provided. In one embodiment, a data storage device comprises a volatile memory, a non-volatile memory, and a controller. The controller is configured to allocate an amount of space in the volatile memory for a history pattern matcher data structure used to predict next read commands from a host to read data stored in the non-volatile memory; determine an accuracy of the predicted next…
Embedded PHY (EPHY) IP core for FPGA
Granted: August 20, 2024
Patent Number:
12066488
The present disclosure generally relates to an embedded physical layer (EPHY) for a field programmable gate array (FPGA). The EPHY for the FPGA is for a testing device that can receive and transmit in both the high speed PHYs, as well as low speed PHYs, such as MIPI PHYS (MPHYs), to meet universal flash storage (UFS) specifications. The testing device with the EPHY for the FPGA provides flexibility to support any specification updates without the need of application specific (ASIC)…
Semiconductor device package mold flow control system and method
Granted: August 13, 2024
Patent Number:
12062625
A semiconductor package includes a substrate having a top planar surface and a semiconductor die mounted on the top planar surface of the substrate. Bond wires electrically connect the semiconductor die to the substrate. Flow control dams are integrally formed with the top planar surface of the substrate and each flow control dam protrudes from the top planar surface of the substrate at a location proximate to the bond wires. The flow control dams reduce the occurrence of wire sweep in…
Systems and methods for dynamically reducing access time of storage device system based on pattern recognition
Granted: August 13, 2024
Patent Number:
12061805
A non-volatile memory system goes into a low-power standby sleep mode to reduce power consumption if a host command is not received within delay period. The duration of this delay period is adjustable. In one set of embodiments, host commands can specify the delay value, the operation types to which it applies, and whether the value is power the current power session or to be used to reset a default value as well. In other aspects, the parameters related to the delay value are kept in a…
System and method for retrimming removable storage devices
Granted: August 13, 2024
Patent Number:
12061791
A data storage device includes a host interface for coupling the data storage device to a host system. The data storage device also includes a device memory and a controller. The controller is configured to determine if a retrim is needed for the data storage device. In accordance with a determination that the retrim is needed, the controller is configured to identify a time to initiate a new trim on the data storage device, and cause the new trim on the data storage device at the time…
Memory device with latch-based neural network weight parity detection and trimming
Granted: August 13, 2024
Patent Number:
12061542
Latch-based methods and apparatus for performing neural network weight parity detection on the die of a non-volatile memory (NVM) array to detect bit flip errors within neural network weight data are described, particularly for use with floating point number values. Upon detection of a parity error in a neural network weight, the erroneous weight is set to zero to trim the corresponding neuron from the network, thus preventing the erroneous value from significantly affecting the network,…
Chip select, command, and address encoding
Granted: August 6, 2024
Patent Number:
12057189
A command/address sequence associated with a read/write operation for a memory device utilizes various existing command/address clock signals in a novel way that obviates the need to utilize the I/O bus. As such, the command/address sequence can be performed in parallel with the DIN/DOUT operations, thereby removing the performance bottleneck that would otherwise be caused by the command and address sequencing. The command/address sequence encodes bit information on first and second…
Three-dimensional memory device with isolated source strips and method of making the same
Granted: August 6, 2024
Patent Number:
12058854
A memory die includes source-select-level electrically conductive strips laterally spaced apart by source-select-level dielectric isolation structures, an alternating stack of word-line-level electrically conductive layers and insulating layers; and source strips located on an opposite side of the source-select-level electrically conductive strips. Each of the source strips has an areal overlap with only a respective one of the source-select-level electrically conductive strips. Memory…
Data storage device encryption
Granted: August 6, 2024
Patent Number:
12058259
This disclosure relates to data storage device (DSD) hardware and, more specifically, to systems and methods for encrypting data stored on a DSD. A DSD comprises a non-volatile storage medium to store multiple file system data objects using block addressing. The multiple file system data objects are addressable by respective ranges of blocks. A device controller is integrated with the DSD and comprises hardware circuitry configured to encrypt data to be stored on the storage medium and…
Use of data latches for plane level compression of soft bit data in non-volatile memories
Granted: August 6, 2024
Patent Number:
12057188
For a non-volatile memory that uses hard bit and soft bit data in error correction operations, to reduce the amount of soft bit data that needs to be transferred from a memory to the controller and improve memory system performance, the soft bit data can be compressed before transfer. After the soft bit data is read and stored into the internal data latches associated with the sense amplifiers, it is compressed within these internal data latches. The compressed soft bit data can then be…
Secondary cross-coupling effect in memory apparatus with semicircle drain side select gate and countermeasure
Granted: August 6, 2024
Patent Number:
12057166
A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and arranged in strings. The memory cells are configured to retain a threshold voltage corresponding to memory states. Each one of the strings has drain-side select gate transistors on a drain-side of the one of the strings including top drain-side select gate transistors connected to bit lines and coupled to the memory cells of the-one of the strings. A control means is…
Memory device with unique read and/or programming parameters
Granted: August 6, 2024
Patent Number:
12057161
The memory device includes a plurality of memory blocks that can individually operate in either a multi-bit per memory cell mode or a single-bit per memory cell mode. Certain voltage parameters during programming and reading are shared between these two operating modes, and certain voltage parameters are unique to each operating mode. One unique voltage parameter is a pass voltage VREADK that is applied to word lines adjacent a selected word line being read. Another unique voltage…
Data storage device and method of access
Granted: August 6, 2024
Patent Number:
12056263
A data storage device and method to selectively enable access to stored user data files. The method includes receiving authentication credential from a user and, in response, retrieving a unique user identifier associated with the authentication credential. The stored user data files on the data storage device each has respective data file identifier. The method includes, for each user, enumerating a directory of stored data files where the data file identifier matches the unique user…
Data storage device with noise injection
Granted: July 30, 2024
Patent Number:
12051482
Noise injection procedures implemented on the die of a non-volatile memory (NVM) array are disclosed. In one example, noise is injected into data by adjusting read voltages to induce bit flips while using feedback to achieve a target amount of information degradation. In another example, random data is iteratively combined with itself to achieve a target percentage of random 1s or 0s, then the random data is combined with data read from the NVM array. In other examples, pixels are…
Soft erase process during programming of non-volatile memory
Granted: July 30, 2024
Patent Number:
12051468
Programming a plurality of non-volatile memory cells includes performing a soft erase process during the programming. The soft erase process includes pre-charging channels of the memory cells and performing an erase operation subsequent to the pre-charging while the channels are at one or more elevated voltages at least partially due to the pre-charging.
Programming of memory cells using a memory string dependent program voltage
Granted: July 30, 2024
Patent Number:
12051467
A storage device including control circuitry, communicatively coupled to a non-volatile memory, configured to perform a programming operation to program a set of memory cells. The control circuitry, when performing the programming operation, may be configured to apply a set of biased program voltages to lines connecting to respective memory cells in an array. The set of biased program voltages may have values that are based on positions of the respective memory cells within the array…
Adaptive automated alarm response system
Granted: July 30, 2024
Patent Number:
12051317
A central control circuit is configured to remotely connect to a plurality of machines over a network. Each machine has a respective user interface to indicate a machine state and enable user input. The central control circuit is configured to receive an alarm code, determine whether the alarm code corresponds to a machine state for which a machine learning application has been trained, and obtain an image from the user interface in response to a determination that the machine learning…
Data storage device with weak bits handling
Granted: July 23, 2024
Patent Number:
12045509
A data storage device includes a non-volatile memory device that includes at least a first wordline having first data and a second wordline sequential and adjacent to the first wordline and a controller coupled to the non-volatile memory device. The controller is configured to receive a write command to program second data to the second wordline, read and store the first data from the first wordline a in a first location prior to programming the second data, program the second data to…
Multi-pass programming operation sequence in a memory device
Granted: July 23, 2024
Patent Number:
12046279
A controller is configured to program the memory cells to a first set of data states in a first programming pass and to a greater second set of data states in a second programming pass. The controller performs the first programming pass on the first word line. The controller then repeats the process of programming a portion of another word line and then comparing an upper tail of an erased data state of the first word line to a critical voltage until the upper tail of the erased data…
