Non-volatile memory integrated with artificial intelligence system for preemptive block management
Granted: September 24, 2024
Patent Number:
12099743
A non-volatile storage apparatus comprises a plurality of memory cells that store host data and two models, a control circuit for writing to and reading from the memory cells, and an inference circuit. The inference circuit uses the first model with a first set of one or more metrics describing current operation of the non-volatile storage apparatus to make a first level prediction about defects and uses the second model with a second set of one or more metrics describing current…
Non-volatile memory with programmable resistance non-data word line
Granted: September 24, 2024
Patent Number:
12099728
In order to lower the peak and average current through the channel (thereby lowering peak and average power consumption) during program-verify, which exhibits a word line dependency, the inventors propose to program dummy memory cells connected to a dummy word line before programming data memory cells connected to a data word line. The additional resistance in the NAND string introduced by the preprogrammed dummy memory cells will cause the peak current, and power consumption, to be…
Ultralow power inference engine with external magnetic field programming assistance
Granted: September 17, 2024
Patent Number:
12093812
An MRAM-based vector multiplication device, such as can be used for inferencing in a neural network, is presented that is ultralow power, low cost, and does not require special on-chip programming. A crosspoint array has an MRAM cell at each crosspoint junction and periphery array circuitry capable of supplying independent input voltages to each word line and reading current on each bit line. Vector multiplication is performed as an in-array multiplication of a vector of input voltages…
Semiconductor device containing bit lines separated by air gaps and methods for forming the same
Granted: September 17, 2024
Patent Number:
12096636
A semiconductor structure includes semiconductor devices located over a substrate, bit lines electrically connected to the semiconductor devices and having a respective reentrant vertical cross-sectional profile within a vertical plane that is perpendicular to a lengthwise direction along which the bit lines laterally extend, and dielectric portions that are interlaced with the bit lines along a horizontal direction that is perpendicular to the lengthwise direction. The dielectric…
Three-dimensional memory device with multiple types of support pillar structures and method of forming the same
Granted: September 17, 2024
Patent Number:
12096632
Two types of support pillar structures are formed in a staircase region of an alternating stack of insulating layers and sacrificial material layers. First-type support pillar structures are formed in areas distal from backside trenches to be subsequently formed, and second-type support pillar structures may be formed in areas proximal to the backside trenches. The second-type support pillar structures may be formed as dielectric support pillar structures, or may be formed with at least…
Transistor circuits including fringeless transistors and method of making the same
Granted: September 17, 2024
Patent Number:
12094944
A field effect transistor includes a gate dielectric and a gate electrode overlying an active region and contacting a sidewall of a trench isolation structure. The transistor may be a fringeless transistor in which the gate electrode does not overlie a portion of the trench isolation region. A planar dielectric spacer plate and a conductive gate cap structure may overlie the gate electrode. The conductive gate cap structure may have a z-shaped vertical cross-sectional profile to contact…
Three-dimensional memory device including hammerhead-shaped word lines and methods of manufacturing the same
Granted: September 17, 2024
Patent Number:
12094943
A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel, a memory film in contact with the vertical semiconductor channel, and a vertical stack of tubular dielectric spacers laterally surrounding the memory film. The tubular dielectric spacers may…
Fast search for leaky word line
Granted: September 17, 2024
Patent Number:
12094550
Technology is disclosed herein for detecting leaky word lines in a non-volatile storage system. The exact leaky word line may be located very rapidly using a divide and conquer approach. First a determination may be made whether at least one word line in a group such as any of the word lines in a block is leaky. This initial determination can be made very quickly. If no word line in the group is leaky, the search can end. However, responsive to a determination that at least one word line…
Non-volatile memory with zone based program speed adjustment
Granted: September 17, 2024
Patent Number:
12094546
In order to decrease the width of threshold voltage distributions of programmed memory cells without unreasonably increasing the time needed to complete programming, a non-volatile memory uses a zone based program speed adjustment. The non-volatile memory starts programming a first set of the non-volatile memory cells until a minimum number of memory cells of the first set of non-volatile memory cells reach a first threshold voltage. In response to the minimum number of memory cells…
Non-volatile memory with differential temperature compensation for super page programming
Granted: September 17, 2024
Patent Number:
12094537
A system has been described that performs differential temperature compensation based on a differential between the temperature at time of programming and temperature at time of reading for a set of data. Differential temperature compensation is useful for bulk programming/reading (e.g., many pages of data) and/or programming/reading super pages of data (multiple pages residing on different memory die).
Hot-cold chunks soft-prediction during programming
Granted: September 17, 2024
Patent Number:
12093558
The present disclosure generally relates to estimating when data to be written will be read or re-written prior to actually writing the data to the memory device. The estimating can be used to smartly route the data to the appropriate memory location at the writing stage or to evict the data from a hot memory location to a colder memory location. To perform the estimating, typical traces or data may be used as may the metadata of the data. Separating data according to the data…
Data storage device and method for swap defragmentation
Granted: September 17, 2024
Patent Number:
12093537
A data storage device stores files in its memory. The files may be logically fragmented in that various parts of a given file may be located in non-continuous logical addresses, which can be disadvantageous. The host can send a request to the data storage device to reduce such logical fragmentation. For example, the host can send a swap command to the data storage device, in response to which the data storage device swaps the logical addresses of data fragments of two different files.…
Read look ahead optimization according to NVMe dataset management hints
Granted: September 17, 2024
Patent Number:
12093130
A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a dataset management (DSM) hint, determine if a second physical memory range associated with a next read operation is located within a threshold number of physical block addresses (PBAs) to a first physical memory range associated with a current read operation, where the next read operation is provided by the DSM hint, and utilize at least a portion of a…
Low line-sensitivity and process-portable reference voltage generator circuit
Granted: September 17, 2024
Patent Number:
12093069
Systems and methods are provided for generating a stable DC reference voltage that has low sensitivity to operating temperature and supply voltage variations and is stable across process corners using complimentary metal-on-semiconductor field-effect transistors (MOSFETS). In an example implementation, a reference voltage generator circuit is provided that includes complimentary MOSFETs including a first complimentary MOSFET connected to a first node and having a first threshold voltage,…
Management of thermal shutdown in data storage devices
Granted: September 10, 2024
Patent Number:
12086438
Methods and apparatus for management of thermal shutdown in data storage devices are provided. One such data storage device includes a non-volatile memory (NVM) including a thermal shutdown temperature indicative of a maximum temperature at which the NVM will retain data stored therein; and a processor coupled to the NVM, the processor configured to: determine whether a temperature at the NVM exceeds the thermal shutdown temperature; start, responsive to the determination that the…
High aspect ratio via fill process employing selective metal deposition and structures formed by the same
Granted: September 10, 2024
Patent Number:
12087626
A method includes forming a semiconductor device, forming a combination of a connection-level dielectric layer and a connection-level metal interconnect structure over the semiconductor device, forming a line-and-via-level dielectric layer over the connection-level dielectric layer, forming an integrated line-and-via cavity through the line-and-via-level dielectric layer over the connection-level metal interconnect structure, selectively growing a conductive via structure consisting…
Non-volatile memory with optimized erase verify sequence
Granted: September 10, 2024
Patent Number:
12087373
An erase process for a group of non-volatile memory cells comprises applying doses of erasing to the group and performing erase verify between pairs of successive doses of erasing. The time needed to complete the erase process can be reduced by optimizing the order of performing erase verify. For example, erase verify can be performed by separately performing erase verify for multiple portions of the group in order from previously determined slowest erasing portion of the group to…
Preventing erase disturb in NAND
Granted: September 10, 2024
Patent Number:
12087371
Technology is disclosed herein for preventing erase disturb in NAND. Erase voltages are applied to a source line and bit lines associated with selected memory cells, while applying an erase enable voltage to word lines connected to the selected cells. Preventing erase disturb may include raising the channel potential of unselected memory cells to a source line voltage that has a sufficiently low magnitude to not erase the unselected cells given a voltage on word lines connected to the…
Control gate signal for data retention in nonvolatile memory
Granted: September 10, 2024
Patent Number:
12087363
The nonvolatile memory includes a plurality of nonvolatile memory cells configured to store multiple data states; a word line connected to a control gate of at least one of the plurality of non-volatile memory cells; a control gate line to supply a control gate signal; a word line switch connected between the word line and the control gate line to control the potential applied to the word line from the control gate line; and a memory controller circuit. The memory controller circuit is…
Systems and methods of compensating degradation in analog compute-in-memory (ACIM) modules
Granted: September 10, 2024
Patent Number:
12086461
Certain aspects of the present disclosure provide techniques for performing compute in memory (CIM) computations. A device comprises a CIM module configured to apply analog weights to input data using multiply-accumulate operations to generate an output. The device further comprises a digital weight storage unit configured to store digital weight references, wherein a digital weight reference corresponds to an analog weight of the analog weights. The device also comprises a device…
