Low line-sensitivity and process-portable reference voltage generator circuit
Granted: September 17, 2024
Patent Number:
12093069
Systems and methods are provided for generating a stable DC reference voltage that has low sensitivity to operating temperature and supply voltage variations and is stable across process corners using complimentary metal-on-semiconductor field-effect transistors (MOSFETS). In an example implementation, a reference voltage generator circuit is provided that includes complimentary MOSFETs including a first complimentary MOSFET connected to a first node and having a first threshold voltage,…
High aspect ratio via fill process employing selective metal deposition and structures formed by the same
Granted: September 10, 2024
Patent Number:
12087628
A semiconductor structure includes a first dielectric material layer, a first metal interconnect structure embedded within the first dielectric material layer and including a first metallic material portion including a first metal, a second dielectric material layer located over the first dielectric material layer, and a second metal interconnect structure embedded within the second dielectric material layer and including an integrated line-and-via structure that includes a second…
High aspect ratio via fill process employing selective metal deposition and structures formed by the same
Granted: September 10, 2024
Patent Number:
12087626
A method includes forming a semiconductor device, forming a combination of a connection-level dielectric layer and a connection-level metal interconnect structure over the semiconductor device, forming a line-and-via-level dielectric layer over the connection-level dielectric layer, forming an integrated line-and-via cavity through the line-and-via-level dielectric layer over the connection-level metal interconnect structure, selectively growing a conductive via structure consisting…
Non-volatile memory with optimized erase verify sequence
Granted: September 10, 2024
Patent Number:
12087373
An erase process for a group of non-volatile memory cells comprises applying doses of erasing to the group and performing erase verify between pairs of successive doses of erasing. The time needed to complete the erase process can be reduced by optimizing the order of performing erase verify. For example, erase verify can be performed by separately performing erase verify for multiple portions of the group in order from previously determined slowest erasing portion of the group to…
Preventing erase disturb in NAND
Granted: September 10, 2024
Patent Number:
12087371
Technology is disclosed herein for preventing erase disturb in NAND. Erase voltages are applied to a source line and bit lines associated with selected memory cells, while applying an erase enable voltage to word lines connected to the selected cells. Preventing erase disturb may include raising the channel potential of unselected memory cells to a source line voltage that has a sufficiently low magnitude to not erase the unselected cells given a voltage on word lines connected to the…
Control gate signal for data retention in nonvolatile memory
Granted: September 10, 2024
Patent Number:
12087363
The nonvolatile memory includes a plurality of nonvolatile memory cells configured to store multiple data states; a word line connected to a control gate of at least one of the plurality of non-volatile memory cells; a control gate line to supply a control gate signal; a word line switch connected between the word line and the control gate line to control the potential applied to the word line from the control gate line; and a memory controller circuit. The memory controller circuit is…
Systems and methods of compensating degradation in analog compute-in-memory (ACIM) modules
Granted: September 10, 2024
Patent Number:
12086461
Certain aspects of the present disclosure provide techniques for performing compute in memory (CIM) computations. A device comprises a CIM module configured to apply analog weights to input data using multiply-accumulate operations to generate an output. The device further comprises a digital weight storage unit configured to store digital weight references, wherein a digital weight reference corresponds to an analog weight of the analog weights. The device also comprises a device…
Management of thermal shutdown in data storage devices
Granted: September 10, 2024
Patent Number:
12086438
Methods and apparatus for management of thermal shutdown in data storage devices are provided. One such data storage device includes a non-volatile memory (NVM) including a thermal shutdown temperature indicative of a maximum temperature at which the NVM will retain data stored therein; and a processor coupled to the NVM, the processor configured to: determine whether a temperature at the NVM exceeds the thermal shutdown temperature; start, responsive to the determination that the…
Devices and methods for optimized fetching of multilingual content in media streaming
Granted: September 3, 2024
Patent Number:
12079511
Systems and methods are disclosed for providing multilingual media files. In certain embodiments, a data storage device includes a controller configured to: receive a command to write data for a media file to a non-volatile memory, wherein the media file includes one or more frames each including a video frame and a plurality of audio frames associated with a plurality of languages; decode using a decoder a first frame of the media file to determine a logical block address (LBA) for a…
Multi-precision digital compute-in-memory deep neural network engine for flexible and energy efficient inferencing
Granted: September 3, 2024
Patent Number:
12079733
Anon-volatile memory structure capable of storing weights for layers of a deep neural network (DNN) and perform an inferencing operation within the structure is presented. An in-array multiplication can be performed between multi-bit valued inputs, or activations, for a layer of the DNN and multi-bit valued weights of the layer. Each bit of a weight value is stored in a binary valued memory cell of the memory array and each bit of the input is applied as a binary input to a word line of…
Data integrity protection of SSDs utilizing streams
Granted: September 3, 2024
Patent Number:
12079504
The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller comprising first random access memory (RAM1), second random access memory (RAM2), and a storage unit divided into a plurality of streams. When a write command is received to write data to a stream, change log data is generated and stored in the RAM1, the previous delta data for the stream is copied from the RAM2 to the RAM1 to be updated with the change log data,…
Bundle multiple timing parameters for fast SLC programming
Granted: September 3, 2024
Patent Number:
12079496
Technology is disclosed herein for managing timing parameters when programming memory cells. Timing parameters used sub-clocks in an MLC program mode may also be used for those same sub-clocks in a first SLC program mode. However, in a second SLC program mode a different set of timing parameters may be used for that set of sub-clocks. Using the same set of timing parameters for the MLC program mode and the first SLC program mode saves storage space. However, the timing parameters for the…
Zoned namespaces in solid-state drives
Granted: September 3, 2024
Patent Number:
12079487
The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller and a media unit. The capacity of the media unit is divided into a plurality of zones. The controller is configured to make informed use of errors by update zone metadata to indicate one or more first logical block addresses were skipped and to indicate the next valid logical block address is available to store data. The controller is further configured to update…
Secure wireless communication system and method
Granted: August 27, 2024
Patent Number:
12075255
A method for secure wireless communication executed by at least one processor of a device. A registration certificate is transmitted to the device by a host, the registration certificate including a Long Term Device Key (LTDK) and being generated by a registration server in response to the registration of the host as authorized to connect to the device. In response to receiving a request for securing a Bluetooth connection between the device and the host, the device transmits the LTDK to…
Embedded PHY (EPHY) IP core for FPGA
Granted: August 20, 2024
Patent Number:
12066488
The present disclosure generally relates to an embedded physical layer (EPHY) for a field programmable gate array (FPGA). The EPHY for the FPGA is for a testing device that can receive and transmit in both the high speed PHYs, as well as low speed PHYs, such as MIPI PHYS (MPHYs), to meet universal flash storage (UFS) specifications. The testing device with the EPHY for the FPGA provides flexibility to support any specification updates without the need of application specific (ASIC)…
Three-dimensional memory device with dielectric isolated via structures and methods of making the same
Granted: August 20, 2024
Patent Number:
12068249
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory stack structures vertically extending through the alternating stack, a perforated dielectric moat structure including a dielectric fill material and vertically extending through the alternating stack. The perforated dielectric moat structure includes, at each level of the insulating layers, two rows of lengthwise dielectric pillar portions laterally extending…
Power reallocation for memory device
Granted: August 20, 2024
Patent Number:
12068041
A data storage device including, in one implementation, a number of memory die packages disposed on a substrate within the data storage device. Each memory die package has a die density that includes one or more memory dies. The die density of each memory die package is configured to provide an even thermal distribution across the number of memory die packages. The respective die densities of two memory of the die packages are different from each other.
Data storage device and method for host multi-command queue grouping based on write-size alignment in a multi-queue-depth environment
Granted: August 20, 2024
Patent Number:
12067293
A data storage device and method are provided for host multi-command queue grouping based on write-size alignment in a multi-queue-depth environment. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to provide a host with an indication of a required amount of data needed to program a set of multi-level cell blocks in the memory; receive an assurance from the host that the host will be providing the data storage device…
Data storage device and method for memory-die-state-aware host command submission
Granted: August 20, 2024
Patent Number:
12067289
A data storage device and method for memory-die-state-aware host command submission are provided. In one embodiment, a data storage device comprises a memory comprising a plurality of memory dies and a controller. The controller is configured to receive a query from a host for a status of a memory die that will be accessed by a command; determine the status of the memory die; and respond to the query by providing the status of the memory die to the host. Other embodiments are possible,…
Data storage device and method for dynamic prediction of random read with low memory consumption
Granted: August 20, 2024
Patent Number:
12067268
A data storage device and method for dynamic prediction of random read with low memory consumption are provided. In one embodiment, a data storage device comprises a volatile memory, a non-volatile memory, and a controller. The controller is configured to allocate an amount of space in the volatile memory for a history pattern matcher data structure used to predict next read commands from a host to read data stored in the non-volatile memory; determine an accuracy of the predicted next…
