Certificates in data storage devices
Granted: October 15, 2024
Patent Number:
12118103
Disclosed herein is a data storage device. A data port transmits data between a host computer system and the data storage device. A non-volatile storage medium stores encrypted user content data and a cryptography engine connected between the data port and the storage medium uses a cryptographic key to decrypt the encrypted user content data. The access controller generates an authorization request for a manager device. The authorization request comprises a certificate. The certificate…
Surface mount technology method and magnetic carrier system
Granted: October 8, 2024
Patent Number:
12114435
A method of soldering one or more components to a substrate includes providing a substrate and applying an amount of solder material to the top planar surface of the substrate. One or more electrical components are mounted to the solder material in a predetermined position and orientation. A carrier is provided having one or more magnets embedded therein. The substrate is positioned above the carrier such that each of the one or more magnets is positioned directly below a corresponding…
Open block boundary group programming for non-volatile memory
Granted: October 8, 2024
Patent Number:
12112814
Technology for open block boundary group programming of non-volatile memory such as NAND. The open block boundary group could potentially be read in response to a request from a host for the data stored in the group. In an aspect, the memory system will determine whether programming a group of memory cells in a selected block will result in an open block. If it will not result in an open block, then the memory system uses a first set of programming parameters to program the group.…
Non-volatile memory with early dummy word line ramp down after precharge
Granted: October 8, 2024
Patent Number:
12112812
Non-volatile memory cells are programmed by pre-charging channels of unselected non-volatile memory cells connected to a selected data word line, boosting the channels of unselected non-volatile memory cells connected to the selected data word line after the pre-charging and applying a program voltage pulse to selected non-volatile memory cells connected to the selected data word line while boosting. The pre-charging includes applying pre-charge voltages to one set of data word lines and…
High speed multi-level cell (MLC) programming in non-volatile memory structures
Granted: October 8, 2024
Patent Number:
12112800
A method for programming a memory array of a non-volatile memory structure, wherein the memory array comprises a population of MLC NAND-type memory cells, and the method comprises: (1) in a first program pulse, programming selected memory cells according to a first programmable state and a second programmable state, and (2) in a second program pulse, programming the selected memory cells according to a third programmable state.
Write performance by relocation during sequential reads
Granted: October 8, 2024
Patent Number:
12112062
A data storage device includes a non-volatile memory device including a memory block including a number of memory dies, and a controller coupled to the non-volatile memory device. A read command is received from an external device and the controller determines whether a read operation associated with the read command is a sequential read operation. One or more relocation operations are performed in response to determining that the read operation is a sequential read operation. The one or…
Adaptive tuning of memory device clock rates based on dynamic parameters
Granted: October 8, 2024
Patent Number:
12112048
The present disclosure generally relates to improving adaptive tuning of different clock rates of a memory device. Rather than clock rates only being determined off of one parameter such as workload, the clock rates now will be determined using multiple parameters. The tuning may be based on system parameters to allow the system to withstand challenges that arise during the operation. The clock frequency table is maintained in the device controller. The table holds the clock frequency of…
Recognition and report of expected write amplification violation
Granted: October 8, 2024
Patent Number:
12112044
The present disclosure generally relates to recognizing a violation of an expected write amplification (WAF) rate and informing a host device of the violation so that the host device may take corrective action and ensure the data storage device does not reach end of life (EOL) earlier than expected. The host can provide the data storage device with an expected lifetime and may additionally provide a benchmark WAF rate. The data storage device compares the actual WAF rate to the benchmark…
Self-aligning heat fins for thermal management
Granted: October 1, 2024
Patent Number:
12108577
A thermal dissipation device for use with electronic assemblies or devices and that includes a heat conductive plate configured to thermally couple to one or more packaged components on a first side of the heat conductive plate. The thermal dissipation device further includes a heat conductive post coupled to a second side of the heat conductive plate. The heat conductive post includes a fin member rotatably coupled to the heat conductive post, which is configured to rotate about an axis…
Three-dimensional memory device containing a pillar contact between channel and source and methods of making the same
Granted: October 1, 2024
Patent Number:
12108597
A semiconductor structure includes a memory die bonded to a logic die. The memory die includes an alternating stack of insulating layers and electrically conductive layers, a semiconductor material layer located on a distal surface of the alternating stack, a dielectric spacer layer located on a distal surface of the semiconductor material layer, memory opening fill structures vertically extending through the alternating stack, through the semiconductor material layer, and at least…
Magnetoresistive memory device and method of operating same using ferroelectric-controlled exchange coupling
Granted: October 1, 2024
Patent Number:
12106790
A magnetoresistive memory cell includes a magnetoresistive layer stack containing a reference layer, a nonmagnetic spacer layer, and a free layer. A ferroelectric material layer having two stable ferroelectric states is coupled to a strain-modulated ferromagnetic layer to alter a sign of magnetic exchange coupling between the strain-modulated ferromagnetic layer and the free layer. The strain-modulated ferromagnetic layer may be the reference layer or a perpendicular magnetic anisotropy…
Parallel fragmented SGL fetching for hiding host turnaround time
Granted: October 1, 2024
Patent Number:
12105990
The present disclosure generally relates to reducing latency when fetching Scatter Gather Lists (SGL). Rather than fetching the required SGLs sequentially regardless of what SGL descriptor is needed, the data storage device fetches all of the last entries of each SGL segment in ahead of time after receiving the command, but before the read data is available. The data storage device will still fetch the previous entries in the segment. Once the last entries are fetched, the last entries…
NAND string read voltage adjustment
Granted: October 1, 2024
Patent Number:
12105963
An apparatus includes a control circuit configured to connect to NAND strings that are connected to bit lines, where each bit line is connected to a plurality of NAND strings in a corresponding plurality of regions of a block. The control circuit is configured to apply a read voltage in read operations directed to NAND strings of the plurality of regions of the block and subsequently adjust the read voltage by a first predetermined amount for read operations directed to NAND strings of a…
Data storage with real time dynamic clock frequency control
Granted: October 1, 2024
Patent Number:
12105574
The present disclosure generally relates to ensuring a data storage device consumes as little power as possible. Different HW modules in the data storage device can operate at different frequencies to ensure any bottleneck HW modules operate at as fast a frequency as possible, while non-bottleneck HW modules operate at slower frequencies and hence, consume less power. The frequency for each HW modules is dynamic and is adjusted based upon detected bottlenecks so that the data storage…
Virtual quality control interpolation and process feedback in the production of memory devices
Granted: October 1, 2024
Patent Number:
12105137
To provide more test data during the manufacture of non-volatile memories and other integrated circuits, machine learning is used to generate virtual test values. Virtual test results are interpolated for one set of tests for devices on which the test is not performed based on correlations with other sets of tests. In one example, machine learning determines a correlation study between bad block values determined at die sort and photo-limited yield (PLY) values determined inline during…
Non-volatile memory with programmable resistance non-data word line
Granted: September 24, 2024
Patent Number:
12099728
In order to lower the peak and average current through the channel (thereby lowering peak and average power consumption) during program-verify, which exhibits a word line dependency, the inventors propose to program dummy memory cells connected to a dummy word line before programming data memory cells connected to a data word line. The additional resistance in the NAND string introduced by the preprogrammed dummy memory cells will cause the peak current, and power consumption, to be…
Three dimensional memory device and method of making thereof by forming channel and memory film after word line replacement
Granted: September 24, 2024
Patent Number:
12101936
A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a memory opening extending through the alternating stack, forming a sacrificial memory opening fill structure in the memory opening, replacing the sacrificial material layers with electrically conductive layers, removing the sacrificial memory opening fill structure selective to the electrically conductive layers, and…
Non-volatile memory with suspension period during programming
Granted: September 24, 2024
Patent Number:
12100461
To remedy short term data retention issues, a system creates a gate to channel voltage differential for non-volatile memory cells between programming and verifying in order to accelerate the effects of the short term data retention issue. That is, the gate to channel voltage differential will accelerate the migrating of electrons out of shallow traps. In some embodiments, the gate to channel voltage differential comprises a higher voltage at the channel in comparison to the gate. In some…
Management of host file-system defragmentation in a data storage device
Granted: September 24, 2024
Patent Number:
12099750
A data storage device having a flash translation layer configured to handle file-system defragmentation in a manner that avoids, reduces, and/or optimizes physical data movement in flash memory. In an example embodiment, the memory controller maintains in a volatile memory thereof a lookaside table that supplants pertinent portions of the logical-to-physical table. Entries of the lookaside table are configured to track source and destination addresses of the host defragmentation requests…
Non-volatile memory integrated with artificial intelligence system for preemptive block management
Granted: September 24, 2024
Patent Number:
12099743
A non-volatile storage apparatus comprises a plurality of memory cells that store host data and two models, a control circuit for writing to and reading from the memory cells, and an inference circuit. The inference circuit uses the first model with a first set of one or more metrics describing current operation of the non-volatile storage apparatus to make a first level prediction about defects and uses the second model with a second set of one or more metrics describing current…
