Three-dimensional NOR array including vertical word lines and discrete memory elements and methods of manufacture
Granted: July 9, 2024
Patent Number:
12035535
A three-dimensional memory device includes an alternating stack of source layers and drain layers located over a substrate, a memory opening vertically extending through the alternating stack, a vertical word line located in the memory opening and vertically extending through each of the source layers and the drain layers of the alternating stack, discrete semiconductor channels contacting horizontal surfaces of a respective vertically neighboring pair of a source layer of the source…
Non-volatile memory with reduced word line switch area
Granted: July 9, 2024
Patent Number:
12032837
A three dimensional non-volatile memory structure includes word lines connected to non-volatile memory cells arranged in blocks. A plurality of word line switches are connected to the word lines and one or more sources of voltage. The word line switches are arranged in groups of X word line switches such that each group of X word line switches is positioned in a line under Y blocks of non-volatile memory cells and has a length that is equal to the width of the Y blocks of non-volatile…
Storage system and method for data-driven intelligent thermal throttling
Granted: July 9, 2024
Patent Number:
12032420
A storage system and method for data-driven intelligent thermal throttling are provided. In one embodiment, the storage system comprises a memory and a controller. The controller is configured to determine a temperature of the memory, estimate a future temperature curve based on the temperature of the memory, and determine a memory throttling delay to apply based on the estimated future temperature curve. Other embodiments are provided.
Three-dimensional memory device with discrete charge storage elements and methods for forming the same
Granted: July 2, 2024
Patent Number:
12029037
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, and memory stack structures extending through the alternating stack. Each of the memory stack structures includes a vertical semiconductor channel, a tunneling dielectric layer, a vertical stack of discrete silicon nitride memory elements located at levels of the electrically conductive layers, and a vertical stack of discrete silicon oxide blocking dielectric…
Three-dimensional memory device with multiple types of support pillar structures and method of forming the same
Granted: July 2, 2024
Patent Number:
12029036
Two types of support pillar structures are formed in a staircase region of an alternating stack of insulating layers and sacrificial material layers. First-type support pillar structures are formed in areas distal from backside trenches to be subsequently formed, and second-type support pillar structures may be formed in areas proximal to the backside trenches. The second-type support pillar structures may be formed as dielectric support pillar structures, or may be formed with at least…
Transistor circuits including fringeless transistors and method of making the same
Granted: July 2, 2024
Patent Number:
12027520
A first field effect transistor contains a first active region including a source region, a drain region and a channel region located between the source region and the drain region, a first gate dielectric overlying the active region, and a first gate electrode overlying the first gate dielectric. A second field effect transistor contains a second active region including a source region, a drain region and a channel region located between the source region and the drain region, a second…
Methods and systems for selectively enabling/disabling memory dies
Granted: June 25, 2024
Patent Number:
12020774
Systems and methods disclosed herein provide for selectively activating or deactivating one or more memory of a memory array, such that related data path logic of deactivated memory dies neither detects nor processes control signals or data signals for data operations. Examples of the systems and methods provided herein operate to detect a first enable signal at a memory die and detect a first data signal on input/output (I/O) receivers of the memory die. Responsive to detecting at least…
Double sense amp and fractional bit assignment in non-volatile memory structures
Granted: June 18, 2024
Patent Number:
12014795
A method for programming a non-volatile memory structure, wherein the method comprises initiating a two-dimensional fractional number of bits-per-cell programming scheme with respect to at least a first memory cell and a second memory cell of a plurality of memory cells of the memory structure, wherein the memory structure comprises: (1) a first memory array that comprises a first population of the plurality of memory cells and associated peripheral circuitry disposed below the first…
Three dimensional memory device containing resonant tunneling barrier and high mobility channel and method of making thereof
Granted: June 18, 2024
Patent Number:
12016179
A memory device includes an alternating stack of insulating layers and control gate layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure containing a memory film and a vertical semiconductor channel located within the memory opening. The memory film contains a resonant tunneling barrier stack, a semiconductor barrier layer, and a memory material layer located between the resonant tunneling barrier stack and the semiconductor…
Field effect transistors with gate fins and method of making the same
Granted: June 18, 2024
Patent Number:
12015084
A field effect transistor includes at least one line trench extending downward from a top surface of a channel region which laterally surrounds or underlies the at least one line trench, a gate dielectric contacting all surfaces of the at least one line trench and including a planar gate dielectric portion that extends over an entirety of a top surface of the channel region, a gate electrode, a source region, and a drain region.
Adaptive semi-circle select gate bias
Granted: June 18, 2024
Patent Number:
12014785
A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and arranged in strings. Each of the strings has a drain-side select gate transistor on a drain-side connected to one of a plurality of bit lines. A control means is coupled to the word lines and the plurality of bit lines and the drain-side select gate transistors. The control means determines a unique select gate voltage for each of a plurality of groupings of the memory…
Method of forming a stepped surface in a three-dimensional memory device and structures incorporating the same
Granted: June 11, 2024
Patent Number:
12010842
A method includes forming a first-tier alternating stack of first insulating layers and first sacrificial material layers, forming a joint dielectric layer over the first-tier alternating stack, such that the joint dielectric layer is thicker than each of the first insulating layers and the first sacrificial material layers, forming a second-tier alternating stack of second insulating layers and second sacrificial material layers over the joint dielectric layer and the first-tier…
Method of making a three-dimensional memory device using composite hard masks for formation of deep via openings
Granted: June 11, 2024
Patent Number:
12010841
An alternating stack of first material layers and second material layers is formed over a substrate. A hard mask layer is formed over the alternating stack. Optionally, an additional hard mask layer can be formed over the hard mask layer. A photoresist layer is applied and patterned, and cavities are formed in the hard mask layer by performing a first anisotropic etch process that transfers a pattern of the openings in the photoresist layer through the hard mask layer. Via openings are…
Three-dimensional memory device with a conductive drain-select-level spacer and methods for forming the same
Granted: June 11, 2024
Patent Number:
12010835
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory opening fill structures vertically extending through the alternating stack in a memory array region, and an electrically conductive spacer extending vertically and electrically connecting a first drain-select-level electrically conductive layer to a second drain-select-level electrically conductive layer.
Three-dimensional memory device containing a capped isolation trench fill structure and methods of making the same
Granted: June 11, 2024
Patent Number:
12009306
A semiconductor structure includes semiconductor devices located on a top surface of a substrate semiconductor layer, lower-level metal interconnect structures embedded in lower-level dielectric material layers, source-level material layers, an alternating stack of insulating layers and electrically conductive layers overlying the source-level material layer, memory stack structures, a vertically alternating sequence of insulating plates and dielectric material plates laterally…
Virtual metrology for feature profile prediction in the production of memory devices
Granted: June 11, 2024
Patent Number:
12009269
To provide more test data during the manufacture of non-volatile memories and other integrated circuits, machine learning is used to generate virtual test values. Virtual test results are interpolated for one set of tests for devices on which the test is not performed based on correlations with other sets of tests. In one example, machine learning determines a correlation study between bad block values determined at die sort and photo-limited yield (PLY) values determined inline during…
Non-volatile memory with shared data transfer latches
Granted: June 11, 2024
Patent Number:
12009049
An apparatus includes a control circuit that is configured to connect to an array of non-volatile memory cells. The control circuit includes a first plurality of data latches configured to connect to non-volatile memory cells of a first plane and a second plurality of data latches configured to connect to non-volatile memory cells of a second plane. The control circuit also includes a shared data transfer data latch configured for transfer of data with the first plurality of data latches…
Three-dimensional memory device including self-aligned drain-select-level isolation structures and method of making thereof
Granted: June 4, 2024
Patent Number:
12004347
An alternating stack of insulating layers and spacer material layers is formed over a substrate. A plurality of arrays of memory opening fill structures is formed through the alternating stack. A plurality of dielectric plates is formed, which laterally surrounds a respective array of memory opening fill structures. Self-aligned drain-select-level isolation structures are formed between a respective neighboring pair of arrays of memory opening fill structures through gaps between…
Cross-point magnetoresistive random memory array and method of making thereof using self-aligned patterning
Granted: June 4, 2024
Patent Number:
12004356
A memory device includes a cross-point array of magnetoresistive memory cells. Each magnetoresistive memory cell includes a vertical stack of a selector-containing pillar structure and a magnetic tunnel junction pillar structure. The lateral spacing between neighboring pairs of magnetoresistive memory cells may be smaller along a first horizontal direction than along a second horizontal direction, and a dielectric spacer or a tapered etch process may be used to provide a pattern of an…
Three-dimensional memory array with dual-level peripheral circuits and methods for forming the same
Granted: June 4, 2024
Patent Number:
12004348
A bonded assembly includes a memory die that is bonded to a logic die. The memory die includes a three-dimensional memory array located on a memory-side substrate, memory-side dielectric material layers located on the three-dimensional memory array and embedding memory-side metal interconnect structures and memory-side bonding pads, a backside peripheral circuit located on a backside surface of the memory-side substrate, and backside dielectric material layers located on a backside of…
