Three-dimensional memory device with isolated source strips and method of making the same
Granted: August 6, 2024
Patent Number:
12058854
A memory die includes source-select-level electrically conductive strips laterally spaced apart by source-select-level dielectric isolation structures, an alternating stack of word-line-level electrically conductive layers and insulating layers; and source strips located on an opposite side of the source-select-level electrically conductive strips. Each of the source strips has an areal overlap with only a respective one of the source-select-level electrically conductive strips. Memory…
Data storage device encryption
Granted: August 6, 2024
Patent Number:
12058259
This disclosure relates to data storage device (DSD) hardware and, more specifically, to systems and methods for encrypting data stored on a DSD. A DSD comprises a non-volatile storage medium to store multiple file system data objects using block addressing. The multiple file system data objects are addressable by respective ranges of blocks. A device controller is integrated with the DSD and comprises hardware circuitry configured to encrypt data to be stored on the storage medium and…
Chip select, command, and address encoding
Granted: August 6, 2024
Patent Number:
12057189
A command/address sequence associated with a read/write operation for a memory device utilizes various existing command/address clock signals in a novel way that obviates the need to utilize the I/O bus. As such, the command/address sequence can be performed in parallel with the DIN/DOUT operations, thereby removing the performance bottleneck that would otherwise be caused by the command and address sequencing. The command/address sequence encodes bit information on first and second…
Use of data latches for plane level compression of soft bit data in non-volatile memories
Granted: August 6, 2024
Patent Number:
12057188
For a non-volatile memory that uses hard bit and soft bit data in error correction operations, to reduce the amount of soft bit data that needs to be transferred from a memory to the controller and improve memory system performance, the soft bit data can be compressed before transfer. After the soft bit data is read and stored into the internal data latches associated with the sense amplifiers, it is compressed within these internal data latches. The compressed soft bit data can then be…
Secondary cross-coupling effect in memory apparatus with semicircle drain side select gate and countermeasure
Granted: August 6, 2024
Patent Number:
12057166
A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and arranged in strings. The memory cells are configured to retain a threshold voltage corresponding to memory states. Each one of the strings has drain-side select gate transistors on a drain-side of the one of the strings including top drain-side select gate transistors connected to bit lines and coupled to the memory cells of the-one of the strings. A control means is…
Memory device with unique read and/or programming parameters
Granted: August 6, 2024
Patent Number:
12057161
The memory device includes a plurality of memory blocks that can individually operate in either a multi-bit per memory cell mode or a single-bit per memory cell mode. Certain voltage parameters during programming and reading are shared between these two operating modes, and certain voltage parameters are unique to each operating mode. One unique voltage parameter is a pass voltage VREADK that is applied to word lines adjacent a selected word line being read. Another unique voltage…
Data storage device and method of access
Granted: August 6, 2024
Patent Number:
12056263
A data storage device and method to selectively enable access to stored user data files. The method includes receiving authentication credential from a user and, in response, retrieving a unique user identifier associated with the authentication credential. The stored user data files on the data storage device each has respective data file identifier. The method includes, for each user, enumerating a directory of stored data files where the data file identifier matches the unique user…
Programming of memory cells using a memory string dependent program voltage
Granted: July 30, 2024
Patent Number:
12051467
A storage device including control circuitry, communicatively coupled to a non-volatile memory, configured to perform a programming operation to program a set of memory cells. The control circuitry, when performing the programming operation, may be configured to apply a set of biased program voltages to lines connecting to respective memory cells in an array. The set of biased program voltages may have values that are based on positions of the respective memory cells within the array…
Data storage device with noise injection
Granted: July 30, 2024
Patent Number:
12051482
Noise injection procedures implemented on the die of a non-volatile memory (NVM) array are disclosed. In one example, noise is injected into data by adjusting read voltages to induce bit flips while using feedback to achieve a target amount of information degradation. In another example, random data is iteratively combined with itself to achieve a target percentage of random 1s or 0s, then the random data is combined with data read from the NVM array. In other examples, pixels are…
Soft erase process during programming of non-volatile memory
Granted: July 30, 2024
Patent Number:
12051468
Programming a plurality of non-volatile memory cells includes performing a soft erase process during the programming. The soft erase process includes pre-charging channels of the memory cells and performing an erase operation subsequent to the pre-charging while the channels are at one or more elevated voltages at least partially due to the pre-charging.
Adaptive automated alarm response system
Granted: July 30, 2024
Patent Number:
12051317
A central control circuit is configured to remotely connect to a plurality of machines over a network. Each machine has a respective user interface to indicate a machine state and enable user input. The central control circuit is configured to receive an alarm code, determine whether the alarm code corresponds to a machine state for which a machine learning application has been trained, and obtain an image from the user interface in response to a determination that the machine learning…
AER and AEN for overlapping cross feature
Granted: July 23, 2024
Patent Number:
12045494
The present disclosure generally relates to validating memory devices. Rather than using debug hardware (HW) to consume, record, and decode firmware (FW) events, standard non-volatile memory express (NVMe) asynchronous event request (AER) and NVMe asynchronous event notification (AEN) is used. The NVMe AER results in initiating a particular function to be performed by a device under test (DUT) and triggering a cross feature (CF) that should at least partially overlap in time with the…
Multi-pass programming operation sequence in a memory device
Granted: July 23, 2024
Patent Number:
12046279
A controller is configured to program the memory cells to a first set of data states in a first programming pass and to a greater second set of data states in a second programming pass. The controller performs the first programming pass on the first word line. The controller then repeats the process of programming a portion of another word line and then comparing an upper tail of an erased data state of the first word line to a critical voltage until the upper tail of the erased data…
Advanced window program-verify
Granted: July 23, 2024
Patent Number:
12046267
A memory apparatus and operating method are provided. The apparatus includes memory cells connected to word lines and disposed in strings and configured to retain a threshold voltage corresponding to data states. A control means is configured to program and verify the memory cells during a program operation. The memory cells associated with predetermined ones of the data states are not verified until the memory cells associated with specific prior ones of the data states finish…
DRAM-less SSD with secure HMB for low latency
Granted: July 23, 2024
Patent Number:
12045516
Aspects of the present disclosure generally relate to data storage devices and related methods that use secure host memory buffers and low latency operations. In one aspect, a controller is configured to fetch a command from a host device, and fetch entry data from a host memory buffer (HMB) of the host device in response to the command from the host device. The HMB is utilized in place of DRAM in the controller so that the data storage device is DRAM-less. In one embodiment, the entry…
In-place write techniques without erase in a memory device
Granted: July 23, 2024
Patent Number:
12045511
The memory device has a plurality of memory blocks including a plurality of memory cells arranged in a plurality of word lines. The memory device also includes control circuitry that is in communication with the plurality of memory blocks. The control circuitry is configured to receive a data write instruction. The control circuitry is further configured to program the memory cells of the memory blocks to an SLC format. In response to the data programmed to the memory cells of the memory…
Data storage device with weak bits handling
Granted: July 23, 2024
Patent Number:
12045509
A data storage device includes a non-volatile memory device that includes at least a first wordline having first data and a second wordline sequential and adjacent to the first wordline and a controller coupled to the non-volatile memory device. The controller is configured to receive a write command to program second data to the second wordline, read and store the first data from the first wordline a in a first location prior to programming the second data, program the second data to…
Data storage device and method for device-initiated hibernation
Granted: July 23, 2024
Patent Number:
12045508
A data storage device and method for device-initiated hibernation are provided. In one embodiment, the data storage device comprises a non-volatile memory and a controller. The controller is configured to: receive, from a host during a set-up phase of a hibernation process, a plurality of write commands with a current state of a volatile memory in the host; store the plurality of write commands in a queue, wherein the plurality of write commands are not executed during the set-up phase…
Combining operations during reset
Granted: July 23, 2024
Patent Number:
12045506
Reset operations impact data storage device latency. Every reset operation involves flushing cache data to the memory device and resetting the front end application specific integrated circuit (ASIC) accelerator/host interface module (HIM). Multiple resets that are performed consecutively waste valuable data storage device resources due to the duplication of the operations that every reset operation performs. Data storage device latency can be improved, as can data storage device idle…
Sideband information over host interface considering link states
Granted: July 23, 2024
Patent Number:
12045501
A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to create one or more thresholds for sending sideband information to a host device, determine that a link state is in a state other than L0, retain sideband information until the one or more thresholds is reached, and send the sideband information to the host device upon reaching the one or more thresholds for a corresponding link state. The one or more thresholds…
