NAND memory with different pass voltage ramp rates for binary and multi-state memory
Granted: July 23, 2024
Patent Number:
12046314
To reduce spikes in the current used by a NAND memory die, different ramp rates are used for the pass voltage applied to unselected word lines during a program operation depending on whether data is stored in a multi-level cell (MLC) format or in a single level cell (SLC) format. These ramp rates can be determined through device characterization and stored as parameter values on the memory die. Different ramp rate interval values can also be used for the pass voltage applied to…
Pre-position dummy word line to facilitate write erase capability of memory apparatus
Granted: July 23, 2024
Patent Number:
12046305
A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines including a dummy word line and other data word lines. The memory cells are disposed in memory holes and configured to retain a threshold voltage. A control means is coupled to the word lines and the memory holes and is configured to determine whether one of the word lines being programmed in a program operation is a particular one of the word lines adjacent the dummy word…
Programming techniques to improve programming time and reduce programming errors
Granted: July 23, 2024
Patent Number:
12046304
A memory device including an array of memory cells arranged in a plurality of word lines is provided. A control circuitry is configured to program the memory cells of a selected word line to a plurality of leading data states in a plurality of programming loops that include programming and verify pulses. The control circuitry is also configured to count a total number of programming loops during programming of the selected word line. The control circuitry is also configured to program at…
Edge word line concurrent programming with verify for memory apparatus with on-pitch semi-circle drain side select gate technology
Granted: July 23, 2024
Patent Number:
12046302
A memory apparatus and method of operation are provided. The memory apparatus includes memory cells connected to one of a plurality of word lines including an edge word line and a plurality of other data word lines. The memory cells are disposed in memory holes organized in rows grouped in a plurality of strings. The rows include full circle rows and semi-circle rows. A control means is configured to program the memory cells connected to the edge word line and in the semi-circle rows of…
Method to optimize first read versus second read margin by switching boost timing
Granted: July 23, 2024
Patent Number:
12046297
An apparatus that comprises a plurality of memory cells and a control circuit coupled to the plurality of memory cells is disclosed. The control circuit is configured to perform a read operation. The read operation includes determining a read condition of a memory cell, where the read condition is of a plurality of read conditions and determining a boost timing for the memory cell, where the boost timing corresponds to the read condition.
Non-volatile memory with short prevention
Granted: July 23, 2024
Patent Number:
12046294
To prevent loss of data due to a word line to memory hole short (or another defect), it is proposed to perform an erase process for a plurality of memory cells, detect that a subset of the plurality of memory cells are slow to erase, and prevent successfully programming for at least some of the memory cells that are slow to erase. This technique uses the erase process to predict future word line to memory hole shorts and prevent programming of memory cells predicted to have a future word…
Sub-block status dependent device operation
Granted: July 23, 2024
Patent Number:
12046289
A storage device is disclosed herein. The storage device comprises: a non-volatile memory, where the non-volatile memory includes a block of N wordlines partitioned into a plurality of sub-blocks; and control circuitry coupled to the N wordlines. The control circuitry is configured to: determine a program status of an unselected sub-block of the plurality of sub-blocks before performing an operation on a selected sub-block of the plurality of sub-blocks; based on determining that the…
Three-dimensional memory device and method of making thereof using double pitch word line formation
Granted: July 23, 2024
Patent Number:
12046285
A vertical repetition of multiple instances of a unit layer stack is formed over a substrate. The unit layer stack includes an insulating layer and a sacrificial material layer. Lateral recesses are formed by removing the sacrificial material layers selective to the insulating layers. Each lateral recess is sequentially fill with at least one conductive fill material and an insulating fill material, and vertically-extending portions of the at least one conductive fill material are…
Field effect transistors having concave drain extension region and method of making the same
Granted: July 16, 2024
Patent Number:
12041770
A field effect transistor includes a source region embedded in a semiconductor material layer, a drain region embedded in the semiconductor material layer and laterally spaced from the source region by a channel, a gate stack including a gate dielectric and a gate electrode, a shallow trench isolation portion embedded in an upper portion of the semiconductor material layer and contacting the drain region and the gate stack, and a concave drain extension region continuously extending…
Cross-point magnetoresistive random memory array and method of making thereof using self-aligned patterning
Granted: July 16, 2024
Patent Number:
12041787
A memory device includes a cross-point array of magnetoresistive memory cells. Each magnetoresistive memory cell includes a vertical stack of a selector-containing pillar structure and a magnetic tunnel junction pillar structure. The lateral spacing between neighboring pairs of magnetoresistive memory cells may be smaller along a first horizontal direction than along a second horizontal direction, and a dielectric spacer or a tapered etch process may be used to provide a pattern of an…
IR drop compensation for sensing memory
Granted: July 16, 2024
Patent Number:
12040010
Technology is disclosed herein for sensing memory cells while compensating for resistance along an electrical pathway between a voltage driver and a control line connected to the memory cells. A control circuit provides a voltage from the voltage driver over a first electrical pathway to a control line in a first block and a second electrical pathway to a control line in a second block. The control circuit senses first memory cells in the first block and the second memory cells in the…
Finding and releasing trapped memory in uLayer
Granted: July 16, 2024
Patent Number:
12039179
The present disclosure generally relates to improving memory management. When valid mSets are relocated via mBlock compaction, the uLayer will have some updates for the mSet and consolidation of the mSet will write the mSet to mBlock once more. The disclosure herein reduces the impact of the problem that the same more frequently updated mSets uRegions are consolidated many times and written to flash where the less updated mSets uRegions become trapped uRegions in the uLayer reducing the…
Three-dimensional NOR array including vertical word lines and discrete memory elements and methods of manufacture
Granted: July 9, 2024
Patent Number:
12035535
A three-dimensional memory device includes an alternating stack of source layers and drain layers located over a substrate, a memory opening vertically extending through the alternating stack, a vertical word line located in the memory opening and vertically extending through each of the source layers and the drain layers of the alternating stack, discrete semiconductor channels contacting horizontal surfaces of a respective vertically neighboring pair of a source layer of the source…
Three dimensional memory device containing dummy word lines and p-n junction at joint region and method of making the same
Granted: July 9, 2024
Patent Number:
12035520
A three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a semiconductor material layer, an inter-tier dielectric layer, and a second alternating stack of second insulating layers and second electrically conductive layers located over the inter-tier dielectric layer. A memory opening vertically extends through the second alternating stack, the inter-tier dielectric layer, and the first…
Non-volatile memory with reduced word line switch area
Granted: July 9, 2024
Patent Number:
12032837
A three dimensional non-volatile memory structure includes word lines connected to non-volatile memory cells arranged in blocks. A plurality of word line switches are connected to the word lines and one or more sources of voltage. The word line switches are arranged in groups of X word line switches such that each group of X word line switches is positioned in a line under Y blocks of non-volatile memory cells and has a length that is equal to the width of the Y blocks of non-volatile…
Storage system and method for data-driven intelligent thermal throttling
Granted: July 9, 2024
Patent Number:
12032420
A storage system and method for data-driven intelligent thermal throttling are provided. In one embodiment, the storage system comprises a memory and a controller. The controller is configured to determine a temperature of the memory, estimate a future temperature curve based on the temperature of the memory, and determine a memory throttling delay to apply based on the estimated future temperature curve. Other embodiments are provided.
Three-dimensional memory device with discrete charge storage elements and methods for forming the same
Granted: July 2, 2024
Patent Number:
12029037
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, and memory stack structures extending through the alternating stack. Each of the memory stack structures includes a vertical semiconductor channel, a tunneling dielectric layer, a vertical stack of discrete silicon nitride memory elements located at levels of the electrically conductive layers, and a vertical stack of discrete silicon oxide blocking dielectric…
Three-dimensional memory device with multiple types of support pillar structures and method of forming the same
Granted: July 2, 2024
Patent Number:
12029036
Two types of support pillar structures are formed in a staircase region of an alternating stack of insulating layers and sacrificial material layers. First-type support pillar structures are formed in areas distal from backside trenches to be subsequently formed, and second-type support pillar structures may be formed in areas proximal to the backside trenches. The second-type support pillar structures may be formed as dielectric support pillar structures, or may be formed with at least…
Transistor circuits including fringeless transistors and method of making the same
Granted: July 2, 2024
Patent Number:
12027520
A first field effect transistor contains a first active region including a source region, a drain region and a channel region located between the source region and the drain region, a first gate dielectric overlying the active region, and a first gate electrode overlying the first gate dielectric. A second field effect transistor contains a second active region including a source region, a drain region and a channel region located between the source region and the drain region, a second…
Methods and systems for selectively enabling/disabling memory dies
Granted: June 25, 2024
Patent Number:
12020774
Systems and methods disclosed herein provide for selectively activating or deactivating one or more memory of a memory array, such that related data path logic of deactivated memory dies neither detects nor processes control signals or data signals for data operations. Examples of the systems and methods provided herein operate to detect a first enable signal at a memory die and detect a first data signal on input/output (I/O) receivers of the memory die. Responsive to detecting at least…
