Semiconductor device containing bit lines separated by air gaps and methods for forming the same
Granted: May 14, 2024
Patent Number:
11984395
A semiconductor structure includes semiconductor devices located over a substrate, bit lines electrically connected to the semiconductor devices and having a respective reentrant vertical cross-sectional profile within a vertical plane that is perpendicular to a lengthwise direction along which the bit lines laterally extend, and dielectric portions that are interlaced with the bit lines along a horizontal direction that is perpendicular to the lengthwise direction. The dielectric…
High speed toggle mode transmitter with capacitive boosting
Granted: May 14, 2024
Patent Number:
11984168
An interface circuit that can operate in toggle mode at data high transfer rates while reducing the self-induced noise is presented. The high speed toggle mode interface supplies a data signal to a data line or other transfer line by a driver circuit. The driver circuit includes a pair of series connected transistors connected between a high supply level and a low supply level, where the data line is supplied from a node between the two transistors. A resistor is connected between one or…
High voltage field effect transistor with vertical current paths and method of making the same
Granted: May 7, 2024
Patent Number:
11978774
A field effect transistor for a high voltage operation can include vertical current paths, which may include vertical surface regions of a pedestal semiconductor portion that protrudes above a base semiconductor portion. The pedestal semiconductor portion can be formed by etching a semiconductor material layer employing a gate structure as an etch mask. A dielectric gate spacer can be formed on sidewalls of the pedestal semiconductor portion. A source region and a drain region may be…
Dynamic sense amplifier supply voltage for power and die size reduction
Granted: May 7, 2024
Patent Number:
11978516
A memory system having a dynamic supply voltage to sense amplifiers. The supply voltage has a higher magnitude when charging inhibited bit lines during a program operation and a lower magnitude when verifying/sensing memory cells. Reducing the magnitude of the supply voltage saves power and/or current. However, if the lower magnitude were used when the inhibited bit lines are charged during the program operations, some of the memory cells that should be inhibited from programming might…
Mixed current-forced read scheme for MRAM array with selector
Granted: May 7, 2024
Patent Number:
11978491
Technology for reading reversible resistivity cells in a memory array when using a current-force read is disclosed. The memory cells are first read using a current-force referenced read. If the current-force referenced read is successful, then results of the current-force referenced read are returned. If the current-force referenced read is unsuccessful, then a current-force self-referenced read (SRR) is performed and results of the current-force SRR are returned. In an aspect this mixed…
Recovery pulses to counter cumulative read disturb
Granted: April 30, 2024
Patent Number:
11972808
A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and disposed in memory holes organized in rows grouped in strings and configured to retain a threshold voltage. The memory cells are connected in series between a drain-side select gate transistor on a drain-side of each of the memory holes and a source-side select gate transistor on a source-side of each of the memory holes. A control means determines whether a downshift…
Method of making a three-dimensional memory device using composite hard masks for formation of deep via openings
Granted: April 30, 2024
Patent Number:
11972954
An alternating stack of first material layers and second material layers can be formed over a semiconductor material layer. A patterning film is formed over the alternating stack, and openings are formed through the patterning film. Via openings are formed through the alternating stack at least to a top surface of the semiconductor material layer by performing a first anisotropic etch process that transfers a pattern of the openings in the patterning film. A cladding liner can be formed…
Verify techniques for current reduction in a memory device
Granted: April 30, 2024
Patent Number:
11972814
The memory device includes a plurality of memory cells, which include a first set of memory cells and a second set of memory cells. A controller is in communication with the memory cells. The controller is configured to, in a first programming pass and then a second programming pass, program the memory cells of the first and second sets to respective final threshold voltages associated with a plurality of programmed data states. The controller is further configured to, in the first…
Read pass voltage dependent recovery voltage setting between program and program verify
Granted: April 30, 2024
Patent Number:
11972810
A memory apparatus and method of operation are provided. The apparatus includes memory cells connected word lines. The memory cells are disposed in strings and configured to retain a threshold voltage. A control means is configured to apply a program voltage to selected ones of the word lines while applying pass voltages to unselected ones of the word lines and ramp down both the selected ones of the plurality of word lines and the unselected ones of the word lines to a recovery voltage…
Selective inhibit bitline voltage to cells with worse program disturb
Granted: April 30, 2024
Patent Number:
11972809
A non-volatile semiconductor memory device includes non-volatile storage elements and one or more control circuits in communication with the non-volatile storage elements. The one or more control circuits are configured to determine for a program iteration of a program operation on a word line whether a condition is met and in response to determining that the condition is met, identify one or more memory cells of the word line that are in an erased state that have a threshold voltage…
Current mirror circuits
Granted: April 30, 2024
Patent Number:
11971736
A circuit is provided that includes a first transistor having a first terminal, a second terminal and a third terminal, and a second transistor comprising a first terminal, a second terminal and a third terminal. The first terminal of the first transistor comprises an input terminal of the circuit, the second terminal of the first transistor is coupled to a power supply bus, and the first transistor conducts a first current. The first terminal of the first transistor comprises an output…
Charge pump current regulation during voltage ramp
Granted: April 30, 2024
Patent Number:
11972807
Technology is disclosed herein for a memory system that regulates charge pump current during a ramp up of the output voltage. The memory systems operates the charge pump in a current regulation mode while the charge pump output voltage ramps up. After the output voltage crosses a threshold voltage, the charge pump is operated in a voltage regulation mode in which the output voltage is regulated to a target output voltage. In one aspect, the memory system generates a random duty cycle…
Read techniques to reduce read errors in a memory device
Granted: April 30, 2024
Patent Number:
11972806
The memory device includes a memory block with a plurality of memory cells, which are programmed to multiple bits per memory cell, arranged in a plurality of word lines. Control circuitry is provided and is configured to read the memory cells of a selected word line. The control circuitry separates the memory cells of the selected word line into a first group of memory cells, which are located on a side of the word line are near a voltage driver, and a second group of memory cells, which…
Non-volatile memory with narrow and shallow erase
Granted: April 30, 2024
Patent Number:
11972805
In a non-volatile memory, to achieve a shallow and tight erased threshold voltage distribution, a process is performed that includes erasing a group of non-volatile memory cells, identifying a first set of the bit lines that are connected to non-volatile memory cells of the group that are erased past a lower limit for erased non-volatile memory cells and identifying a second set of the bit lines that are connected to non-volatile memory cells of the group that are not erased past the…
Techniques for checking vulnerability to cross-temperature read errors in a memory device
Granted: April 30, 2024
Patent Number:
11972804
The memory device includes a memory block with an array of memory cells. The memory device also includes control circuitry that is in communication with the memory cells. The control circuitry is configured to program a group of the memory cells in a programming operation that does not include verify to obtain a natural threshold voltage (nVt) distribution, calculate an nVt width of the nVt distribution, compare the nVt width to a threshold, and identify the memory block as being…
Word line zone dependent pre-charge voltage
Granted: April 30, 2024
Patent Number:
11972803
A memory device that uses different programming parameters base on the word line(s) to be programmed is described. The programming parameter PROGSRC_PCH provides a pre-charge voltage to physical word lines. In some instances, the PROGSRC_PCH voltage is decoupled, and a new PROGSRC_PCH represents an adjusted (e.g., increased) pre-charge voltage for a certain physical word line or word line zone (i.e., predetermined group of word lines). Using different PROGSRC_PCH voltages can limit or…
Program voltage dependent program source levels
Granted: April 30, 2024
Patent Number:
11972801
A non-volatile semiconductor memory device, described herein, comprises non-volatile storage elements and one or more control circuits in communication with the non-volatile storage elements. The one or more control circuits are configured to, during a program iteration of a program operation, determine whether a program voltage level of the program iteration exceeds a threshold program voltage level and in response to the determination, identify a set of voltage levels to apply to a…
Cross-point array refresh scheme
Granted: April 30, 2024
Patent Number:
11972787
Technology is disclosed herein for refreshing threshold switching selectors in programmable resistance memory cells in cross-point memory arrays. The Vt of the threshold switching selector may drift over time. The memory system resets the Vt of the threshold switching selectors with a selector refresh operation and uses a separate data refresh operation to refresh data in programmable resistance memory elements. The data refresh operation itself may also refresh the selector. However,…
On-the-fly compression scheme for soft bit data in non-volatile memory
Granted: April 30, 2024
Patent Number:
11971829
For a non-volatile memory that uses hard bit and a soft bit data in error correction operations, an on-the-fly compression scheme is used for the soft bit data. As soft bit data is transferred to a memory's input-output interface, the soft bit data is compressed prior to transmission to the an ECC engine memory controller, while hard bit data is transferred in un-compressed form.
Architecture and data path options for compression of soft bit data in non-volatile memories
Granted: April 30, 2024
Patent Number:
11971826
For a non-volatile memory that uses hard bit and a soft bit data in error correction operations, architectures are introduced for the compression of the soft bit data to reduce the amount of data transferred over the memory's input-output interface. For a memory device with multiple planes of memory cells, the internal global data bus is segmented and a data compression circuit associated with each segment. This allows soft bit data from a cache buffer of a plane using one segment to…
