Post-write read techniques to improve programming reliability in a memory device
Granted: April 30, 2024
Patent Number:
11972815
The memory device includes a controller that is configured to program a plurality of memory cells of a selected word line in a plurality of programming loops and count the number of programming loops to complete programming. The controller is also configured to compare the number of programming loops to complete programming of the memory cells of the selected word line to at least one of a predetermined upper limit and a predetermined lower limit to determine if a plane containing the…
Ferroelectric devices including a single crystalline ferroelectric layer and method of making the same
Granted: April 30, 2024
Patent Number:
11973123
A semiconductor structure includes an active region including a source region, a drain region, and a channel region extending between the source region and the drain region, a gate stack, and a gate dielectric layer located between the gate stack and the active region. The gate stack includes an electrically conductive gate electrode and a single crystalline III-nitride ferroelectric plate located between the electrically conductive gate electrode and the gate dielectric layer, and an…
Non-volatile memory with efficient signal routing
Granted: April 30, 2024
Patent Number:
11973044
An integrated memory assembly comprises a control die bonded to a memory die. The memory die includes multiple non-volatile memory structures (e.g., planes, arrays, groups of blocks, etc.), each comprising a stack of alternating conductive and dielectric layers forming staircases at one or more edges of the non-volatile memory structures. The non-volatile memory structures are positioned with gaps between the non-volatile memory structures such that the gaps separate the staircases of…
Three-dimensional memory device including stairless word line contact structures and method of making the same
Granted: April 30, 2024
Patent Number:
11973026
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings located in a memory array region and vertically extending through the alternating stack, memory opening fill structures located in the memory openings, and laterally-isolated contact via assemblies located in a contact region. Each of the laterally-isolated contact via assemblies includes a contact via structure contacting a top…
Method of making a three-dimensional memory device using composite hard masks for formation of deep via openings
Granted: April 30, 2024
Patent Number:
11972954
An alternating stack of first material layers and second material layers can be formed over a semiconductor material layer. A patterning film is formed over the alternating stack, and openings are formed through the patterning film. Via openings are formed through the alternating stack at least to a top surface of the semiconductor material layer by performing a first anisotropic etch process that transfers a pattern of the openings in the patterning film. A cladding liner can be formed…
Programmable ECC for MRAM mixed-read scheme
Granted: April 30, 2024
Patent Number:
11972822
Technology is disclosed for a fast ECC engine for a mixed read of MRAM cells. A codeword read from MRAM cells using a referenced read is decoded using a first ECC mode. If decoding passes, results are provided to a host. If decoding fails, a self-referenced read (SRR) is performed. The data read using the SRR is decoded with a second ECC mode that is capable of correcting a greater number of bits than the first ECC mode. The second ECC mode may have a higher mis-correction rate than the…
Non-volatile memory with tier-wise ramp down after program-verify
Granted: April 30, 2024
Patent Number:
11972820
Memory cells are arranged as NAND strings to form a block divided into sub-blocks, and each NAND string includes a dummy memory cell connected to a dummy word line. Memory cells are programmed by applying programming pulses to a selected word line in a selected sub-block with program-verify performed between pulses. Unselected NAND strings are inhibited from programming by boosting channels of the unselected NAND strings in the selected sub-block from a positive pre-charge voltage to a…
Non-volatile memory with one sided phased ramp down after program-verify
Granted: April 30, 2024
Patent Number:
11972819
In a non-volatile memory system that performs programming of selected memory cells (in coordination with pre-charging and boosting of channels for unselected memory cells) and program-verify to determine whether the programming was successful, the system transitions from program-verify to the next dose of programming by concurrently lowering a voltage applied to a selected word line and voltages applied to word lines on a first side of the selected word line at the conclusion of…
Refresh frequency-dependent system-level trimming of verify level offsets for non-volatile memory
Granted: April 30, 2024
Patent Number:
11972818
A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to word lines. The memory cells are disposed in strings and configured to retain a threshold voltage corresponding to data states. A control means is configured to apply verification pulses of program verify voltages each associated with one of the data states to selected ones of the word lines to determine whether the memory cells connected thereto have the threshold voltage above…
State look ahead quick pass write algorithm to tighten ongoing natural threshold voltage of upcoming states for program time reduction
Granted: April 30, 2024
Patent Number:
11972817
A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines. The memory cells are disposed in strings and are configured to retain a threshold voltage corresponding to data states. A control means is configured to apply verification pulses of program verify voltages each associated with one of the data states to selected ones of the word lines to determine whether the memory cells connected thereto have the threshold voltage above…
Verify techniques for current reduction in a memory device
Granted: April 30, 2024
Patent Number:
11972814
The memory device includes a plurality of memory cells, which include a first set of memory cells and a second set of memory cells. A controller is in communication with the memory cells. The controller is configured to, in a first programming pass and then a second programming pass, program the memory cells of the first and second sets to respective final threshold voltages associated with a plurality of programmed data states. The controller is further configured to, in the first…
Systems and methods for adapting sense time
Granted: April 30, 2024
Patent Number:
11972813
A memory device with adaptive sense time tables is disclosed. In order to maintain a desired (initial or preset) threshold voltage distribution, the sense time is adjusted as the program-erase cycle count increases. The program-erase cycle process tends to wear down memory cells, causing the QPW window to expand and the threshold voltage to widen. However, by adjusting (i.e., reducing) the sense time for increased program-erase cycles, the QPW window and the threshold voltage can be at…
Non-volatile memory with data refresh based on data states of adjacent memory cells
Granted: April 30, 2024
Patent Number:
11972812
A memory system identifies memory cells connected to a common word line that have had their threshold voltage unintentionally drift lower than programmed by determining whether memory cells meet two criteria: (1) the memory cells have threshold voltages within an offset of a read compare voltage of a data state; and (2) adjacent memory cells (connected to word lines that are adjacent to the common word line) are in one or more low data states. For those memory cells meeting the two…
Read pass voltage dependent recovery voltage setting between program and program verify
Granted: April 30, 2024
Patent Number:
11972810
A memory apparatus and method of operation are provided. The apparatus includes memory cells connected word lines. The memory cells are disposed in strings and configured to retain a threshold voltage. A control means is configured to apply a program voltage to selected ones of the word lines while applying pass voltages to unselected ones of the word lines and ramp down both the selected ones of the plurality of word lines and the unselected ones of the word lines to a recovery voltage…
Selective inhibit bitline voltage to cells with worse program disturb
Granted: April 30, 2024
Patent Number:
11972809
A non-volatile semiconductor memory device includes non-volatile storage elements and one or more control circuits in communication with the non-volatile storage elements. The one or more control circuits are configured to determine for a program iteration of a program operation on a word line whether a condition is met and in response to determining that the condition is met, identify one or more memory cells of the word line that are in an erased state that have a threshold voltage…
Recovery pulses to counter cumulative read disturb
Granted: April 30, 2024
Patent Number:
11972808
A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and disposed in memory holes organized in rows grouped in strings and configured to retain a threshold voltage. The memory cells are connected in series between a drain-side select gate transistor on a drain-side of each of the memory holes and a source-side select gate transistor on a source-side of each of the memory holes. A control means determines whether a downshift…
Charge pump current regulation during voltage ramp
Granted: April 30, 2024
Patent Number:
11972807
Technology is disclosed herein for a memory system that regulates charge pump current during a ramp up of the output voltage. The memory systems operates the charge pump in a current regulation mode while the charge pump output voltage ramps up. After the output voltage crosses a threshold voltage, the charge pump is operated in a voltage regulation mode in which the output voltage is regulated to a target output voltage. In one aspect, the memory system generates a random duty cycle…
Read techniques to reduce read errors in a memory device
Granted: April 30, 2024
Patent Number:
11972806
The memory device includes a memory block with a plurality of memory cells, which are programmed to multiple bits per memory cell, arranged in a plurality of word lines. Control circuitry is provided and is configured to read the memory cells of a selected word line. The control circuitry separates the memory cells of the selected word line into a first group of memory cells, which are located on a side of the word line are near a voltage driver, and a second group of memory cells, which…
Mixing normal and reverse order programming in NAND memory devices
Granted: April 23, 2024
Patent Number:
11967382
The memory device includes a plurality of dies, and each die includes a plurality of blocks with a plurality of word lines. Some of the word lines are arranged in a plurality of exclusive OR (XOR) sets with each XOR set containing word lines in the same positions across the plurality of dies. The memory device further includes a controller that is configured to program the word lines of the blocks of at least one of the dies in a first programming direction. The controller is further…
Three-dimensional memory device containing on-pitch drain select level structures and methods of making the same
Granted: April 23, 2024
Patent Number:
11968825
A three-dimensional memory device includes an alternating stack of insulating layers and word-line-level electrically conductive layers located over a substrate, and a vertical layer stack located over the alternating stack, the vertical layer stack including an insulating cap layer, drain select electrodes, and a drain-select-level insulating layer. The drain select electrodes are laterally spaced apart from each other by drain-select-level isolation structures. Memory stack structures…
