Sub-block mode for non-volatile memory
Granted: February 6, 2024
Patent Number:
11894064
The memory device includes a block with a plurality of memory cells arranged in a plurality of data word lines, which are arranged in sub-blocks that are not separated from one another by physical joints or by dummy word lines. A controller is configured to erase the memory cells of a selected sub-block of the plurality of sub-blocks without erasing the memory cells of the unselected sub-blocks. The controller reads data of the edge one word lines of the unselected sub-blocks adjacent…
Three-dimensional memory device containing amorphous and crystalline blocking dielectric layers
Granted: February 6, 2024
Patent Number:
11894298
A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, where each of the memory opening fill structures contains a memory film and a vertical semiconductor channel that extend vertically, and each memory film includes a crystalline blocking dielectric metal oxide layer, and a…
EP cycling dependent asymmetric/symmetric VPASS conversion in non-volatile memory structures
Granted: February 6, 2024
Patent Number:
11894081
A method for programming a target memory cell of a memory array of a non-volatile memory system, the method comprises determining a total number of erase/programming (EP) cycles that were applied previously to the memory cell and, (1) if the determined total number of cycles does not exceed a threshold value, applying an asymmetric programming scheme, and, (2) if the determined total number of cycles exceeds the threshold value, applying a symmetric programming scheme. Further, a…
Time-tagging read levels of multiple wordlines for open block data retention
Granted: February 6, 2024
Patent Number:
11894080
An apparatus disclosed herein comprises: a plurality of memory cells and a control circuit coupled to the plurality of memory cells. The control circuit is configured to: acquire a first set of read levels on a wordline of a first block of pages of memory cells; acquire a second set of read levels on a first wordline of a second block of pages of a second set of memory cells in response to determining that the fail bit count of the page after a read operation is above the threshold…
Self-diagnostic smart verify algorithm in user mode to prevent unreliable acquired smart verify program voltage
Granted: February 6, 2024
Patent Number:
11894077
A memory apparatus and operating method are provided. The apparatus includes memory cells connected to word lines and disposed in memory holes and configured to retain a threshold voltage. The memory holes are organized in rows grouped in strings. A control means is coupled to the word lines and the memory holes and programs the memory cells associated with a first one of the strings in a program operation and acquire a smart verify programming voltage in a smart verify operation…
Proactive refresh of edge data word line for semi-circle drain side select gate
Granted: February 6, 2024
Patent Number:
11894073
A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to one of a plurality of word lines including at least one edge word line and a plurality of other data word lines. The memory cells are arranged in strings and configured to retain a threshold voltage corresponding to one of a plurality of data states. The memory apparatus also includes a control means coupled to the plurality of word lines and the strings. The control means is…
Two-side staircase pre-charge in sub-block mode of three-tier non-volatile memory architecture
Granted: February 6, 2024
Patent Number:
11894072
A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and disposed in strings. A control means is coupled to the word lines and the strings and is configured to ramp a voltage applied to a selected one of the word lines from a verify voltage to a reduced voltage during a program-verify portion of a program operation. The control means successively ramps voltages applied to each of a plurality of neighboring ones of the word…
Non-volatile memory with differential temperature compensation for bulk programming
Granted: February 6, 2024
Patent Number:
11894071
A system has been described that performs differential temperature compensation based on a differential between the temperature at time of programming and temperature at time of reading for a set of data. Differential temperature compensation is useful for bulk programming/reading (e.g., many pages of data) and/or programming/reading super pages of data (multiple pages residing on different memory die).
Efficient sensing of soft bit data for non-volatile memory
Granted: February 6, 2024
Patent Number:
11894068
A non-volatile memory combines a hard bit and a soft bit read into a single, efficient soft sense sequence by using two sense per state level to improve read time efficiency. Rather than a standard hard bit read, where two soft bit reads are performed, offset above and below the hard bit read value, the hard bit read is shifted so that it reliable senses one state but less reliably senses the other state and soft bit data is only determined for the less reliably sensed state. This…
Method to fix cumulative read induced drain side select gate downshift in memory apparatus with on-pitch drain side select gate
Granted: February 6, 2024
Patent Number:
11894067
A memory apparatus and method of operation are provided. The memory apparatus includes memory cells configured to retain a threshold voltage. The memory cells are connected to one of a plurality of word lines and are arranged in strings comprising a plurality of blocks. A control means is coupled to the plurality of word lines and the strings and is configured to periodically determine a read frequency metric associated with a plurality of read operations of one of the plurality of…
Semi-circle drain side select gate maintenance by selective semi-circle dummy word line program
Granted: February 6, 2024
Patent Number:
11894062
A memory apparatus and method of operation are provided. The apparatus includes apparatus including memory cells connected to word lines including at least one dummy word line and data word lines. The memory cells are arranged in strings and are configured to retain a threshold voltage. The apparatus also includes a control means coupled to the word lines and the strings and configured to identify ones of the memory cells connected to the at least one dummy word line with the threshold…
Non-volatile memory with efficient word line hook-up
Granted: February 6, 2024
Patent Number:
11894056
A three dimensional non-volatile memory structure includes word lines connected to non-volatile memory cells arranged in blocks. A plurality of word line switches are connected to the word lines and one or more sources of voltage. The word line switches are arranged in groups of X word line switches such that each group of X word line switches is positioned in a line under Y blocks of non-volatile memory cells and has a length that is equal to the width of the Y blocks of non-volatile…
Temperature-dependent word line voltage and discharge rate for refresh read of non-volatile memory
Granted: February 6, 2024
Patent Number:
11894051
A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to one of a plurality of word lines. The memory cells are disposed in strings and configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is coupled to the plurality of word lines and the strings and is configured to apply a read voltage to a selected ones of the plurality of word lines during a read operation and ramp down to a…
First fire and cold start in memories with threshold switching selectors
Granted: February 6, 2024
Patent Number:
11894037
In a memory array with a cross-point structure, at each cross-point junction a programmable resistive memory element, such as an MRAM memory cell, is connected in series with a threshold switching selector, such as an ovonic threshold switch. The threshold switching selector switches to a conducting state when a voltage above a threshold voltage is applied. When powered down for extended periods, the threshold voltage can drift upward. If the drift is excessive, this can make the memory…
Three-dimensional memory device with separated contact regions and methods for forming the same
Granted: January 30, 2024
Patent Number:
11889694
A memory die includes an alternating stack of insulating layers and electrically conductive layers through which memory opening fill structures vertically extend. The memory die includes at least three memory array regions interlaced with at least two contact regions, or at least three contact regions interlaced with at least two memory array regions in the same memory plane. A logic die including at least two word line driver regions can be bonded to the memory die. The interlacing of…
Three-dimensional memory device with separated source-side lines and method of making the same
Granted: January 30, 2024
Patent Number:
11889684
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over at least one source layer, and groups of memory opening fill structures vertically extending through the alternating stack. Each memory opening fill structure can include a vertical stack of memory elements and a vertical semiconductor channel. A plurality of source-side select gate electrodes can be laterally spaced apart by source-select-level dielectric…
Quick pass write programming techniques in a memory device
Granted: January 30, 2024
Patent Number:
11887677
The memory device includes a controller that is configured to program the memory cells of a selected word line in a plurality of program-verify iterations. During a verify portion at least one of the program-verify iterations, the controller determines a threshold voltage of at least one memory cell relative to a first verify low voltage VL1, a second verify low voltage VL2, and a verify high voltage VH associated with a data state being programmed. The controller also maintains a count…
Utilizing data pattern effect to control read clock timing and bit line kick for read time reduction
Granted: January 30, 2024
Patent Number:
11887674
A memory apparatus and method of operation is provided. The apparatus includes memory cells each connected to one of a plurality of word lines. The memory cells are disposed in strings coupled to one of a plurality of bit lines and are configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is configured to read each of the memory cells in a read operation. For each one of the memory cells, the control means is also configured to…
Controlling bit line pre-charge voltage separately for multi-level memory cells and single-level memory cells to reduce peak current consumption
Granted: January 30, 2024
Patent Number:
11887670
Apparatuses and techniques are described for controlling a bit line pre-charge voltage in a program operation based on a number of bits per cell, with a goal to reduce peak current consumption. In one aspect, the ramp up of a bit line voltage to an inhibit level is optimized according to the number of bits per cell. The ramp up can involve increasing the bit line voltage from an initial level to a target voltage at a regulated rate, then increasing the bit line voltage from the target…
Lateral transistors for selecting blocks in a three-dimensional memory array and methods for forming the same
Granted: January 23, 2024
Patent Number:
11882702
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory opening fill structures including a respective vertical semiconductor channel and a respective vertical stack of memory elements extending through the alternating stack in a memory array region, via contact structures contacting the stepped surfaces of the electrically conductive layers at each step in a staircase region, and a vertical stack of access…
