Lateral transistors for selecting blocks in a three-dimensional memory array and methods for forming the same
Granted: January 23, 2024
Patent Number:
11882702
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory opening fill structures including a respective vertical semiconductor channel and a respective vertical stack of memory elements extending through the alternating stack in a memory array region, via contact structures contacting the stepped surfaces of the electrically conductive layers at each step in a staircase region, and a vertical stack of access…
Non-volatile memory with engineered channel gradient
Granted: January 23, 2024
Patent Number:
11881271
To save power during a read process, NAND strings of each sub-block of a block have independently controlled source side select lines connected to source side select gates and drain side select lines connected to drain side select gates so that NAND strings of unselected sub-blocks can float and not draw current. To prevent read disturb in NAND strings of unselected sub-blocks, after all word lines are raised to a pass gate voltage, unselected word lines nearby the selected word line are…
Neighbor bit line coupling enhanced gate-induced drain leakage erase for memory apparatus with on-pitch semi-circle drain side select gate technology
Granted: January 23, 2024
Patent Number:
11881266
A memory apparatus and method of operation are provided. The memory apparatus includes memory cells connected to word lines and disposed in memory holes organized in rows grouped in strings. The memory cells are configured to retain a threshold voltage. The rows include full circle rows and semi-circle rows in which the memory holes are partially cut by a slit half etch. The memory holes of the semi-circle rows are coupled semi-circle bit lines and the memory holes of the full circle…
Three-dimensional memory device including laterally-undulating memory material layers and methods for forming the same
Granted: January 16, 2024
Patent Number:
11877452
A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel and a memory material layer. A vertical stack of insulating material portions can be provided at levels of the insulating layers to provide a laterally-undulating profile to the…
Three-dimensional memory device with electrically conductive layers containing vertical tubular liners and methods for forming the same
Granted: January 16, 2024
Patent Number:
11877446
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, and memory opening fill structures located within the memory openings. Each of the electrically conductive layers includes a metallic fill material layer and a plurality of vertical tubular metallic liners laterally surrounding a respective one of the memory opening fill structures and located between…
Field effect transistors with reduced gate fringe area and method of making the same
Granted: January 16, 2024
Patent Number:
11876096
A semiconductor structure includes at least two field effect transistors. A gate strip including a plurality of gate dielectrics and a gate electrode strip can be formed over a plurality of semiconductor active regions. Source/drain implantation is conducted using the gate strip as a mask. The gate strip is divided into gate electrodes after the implantation.
Systems and methods for staggering read operation of sub-blocks
Granted: January 16, 2024
Patent Number:
11875842
A memory device with one or more planes having sub-blocks is disclosed. The memory device may further include a voltage switch transistor for each of sub-blocks. Additionally, the memory device may further include a row decoder for each of sub-blocks. As a result, an operation to two sub-blocks can be performed at different times. For example, using a row decoder and voltage switch transistor, a sub-block can be initially read, followed by a subsequent read of another sub-block using a…
Loop dependent word line ramp start time for program verify of multi-level NAND memory
Granted: January 16, 2024
Patent Number:
11875043
To reduce spikes in the current used by a NAND memory die during a write operation using smart verify, different amounts of delay are introduced into the loops of the programing algorithm. Depending on the number of verify levels following a programming pulse, differing amounts of wait time are used before biasing a selected word line to the verify levels or levels. For example, if only a single verify level is used, a shorter delay is used than if two verify levels are used.
Bonded assembly including inter-die via structures and methods for making the same
Granted: January 9, 2024
Patent Number:
11869877
A bonded assembly includes a first semiconductor die and a second semiconductor die that are bonded to each other by dielectric-to-dielectric bonding. First conductive via structures vertically extend through the second semiconductor die and a respective subset of the first dielectric material layers in the first semiconductor die, and contact a respective first metal interconnect structure in the first semiconductor die. Second conductive via structures vertically extend through a…
Three-dimensional memory device including low-k drain-select-level isolation structures and methods of forming the same
Granted: January 9, 2024
Patent Number:
11871580
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, an array of memory opening fill structures located within an array of memory openings vertically extending through the alternating stack, and a drain-select-level isolation structure vertically extending through drain-select-level electrically conductive layers between two rows of memory opening fill structures. The drain-select-level isolation…
Systems and methods of reducing detection error and duty error in memory devices
Granted: January 9, 2024
Patent Number:
11869619
Systems and methods are provided that combine a write duty cycle adjuster with write training to reduce detection and duty cycle errors in memory devices. Various embodiments herein perform write duty cycle adjuster operations to adjust a duty cycle of a clock signal that coordinates a data signal with a data operation on the memory device based on an error in the duty cycle, and performs write training operations to detect a skew between the data signal and the clock signal and adjust a…
Memory cell sensing by charge sharing between sensing nodes
Granted: January 9, 2024
Patent Number:
11869600
Memory cell sensing by charge sharing between two sense nodes is disclosed. A first sense node and a second sense node are pre-charged and the second node is discharged initiating charge sharing between the first sense node and the second sense node that results in an improved sense margin. Sensing circuitry disclosed herein may include one or more pre-charge circuits, sense enable circuits, and charge-sharing circuits. The increased sense margin achieved by sensing circuitry disclosed…
Audit techniques for read disturb detection in an open memory block
Granted: January 2, 2024
Patent Number:
11862260
Read disturb audit techniques that include algorithmically applying audit verify voltages to erased wordlines in an open memory block are described. In an audit verify technique, a pass-through voltage ensured to be higher than any threshold voltage of any cell is applied to each wordline in an open memory block that includes one or more programmed memory cells, and an audit verify voltage lower than the pass-through voltage is applied to each erased wordline. A first bit count…
Non-volatile memory with plane independent screening
Granted: January 2, 2024
Patent Number:
11862256
A non-volatile storage apparatus that comprises a plurality of planes of non-volatile memory cells is capable of concurrently programming memory cells in multiple planes. In order to screen for failure of the programming process in a subset of planes, the completion of programming of a fastest plane to a particular data state is used as a trigger to test for program failure of other planes to a different data state. In one embodiment, the test for program failure of other planes to the…
Non-volatile memory with staggered ramp down at the end of pre-charging
Granted: January 2, 2024
Patent Number:
11862249
In order to inhibit memory cells from programming and mitigate program disturb, the memory pre-charges channels of NAND strings connected to a common set of control lines by applying positive voltages to the control lines and applying voltages to a source line and bit lines connected to the NAND strings. The control lines include word lines and select lines. The word lines include an edge word line. The memory ramps down the positive voltages applied to the control lines, including…
Three-dimensional memory device including low-k drain-select-level isolation structures and methods of forming the same
Granted: December 26, 2023
Patent Number:
11856765
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, an array of memory opening fill structures located within an array of memory openings vertically extending through the alternating stack, and a drain-select-level isolation structure vertically extending through drain-select-level electrically conductive layers between two rows of memory opening fill structures. The drain-select-level isolation…
Word line zoned adaptive initial program voltage for non-volatile memory
Granted: December 26, 2023
Patent Number:
11854620
An apparatus is provided that includes a plurality of word lines that include a plurality of word line zones, a plurality of non-volatile memory cells coupled to the plurality of word lines, and a control circuit coupled to the non-volatile memory cells. The control circuit is configured to determine a corresponding initial program voltage for each of the word line zones. Each corresponding initial program voltage is determined based on a number of program erase cycles.
Aggressive quick-pass multiphase programming for voltage distribution state separation in non-volatile memory
Granted: December 26, 2023
Patent Number:
11854611
A multiphase programming scheme for programming a plurality of memory cells of a data storage system includes a first programming phase in which a first set of voltage distributions of the plurality of memory cells is programmed by applying a first plurality of program pulses to word lines of the plurality of memory cells, and a second programming phase in which a second set of voltage distributions is programmed by applying a second plurality of program pulses to the word lines of the…
Signal amplification in MRAM during reading, including a pair of complementary transistors connected to an array line
Granted: December 26, 2023
Patent Number:
11854592
A control circuit is configured to connect to a cross-point memory array in which each conductive line, such as a bit line or word line, is connected to a transistor pair comprising a pMOSFET in parallel with an nMOSFET. When selecting a memory cell to be read, a voltage of a first conductive line may be pulled up using the pMOSFET in a conductive state while the nMOSFET is in a non-conductive state. Further, when reading the selected memory cell, the parallel nMOSFET of the first…
Three-dimensional memory device with a columnar memory opening arrangement and method of making thereof
Granted: December 19, 2023
Patent Number:
11849578
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a plurality of periodic two-dimensional arrays of memory openings vertically extending through the alternating stack, a plurality of periodic two-dimensional arrays of memory opening fill structures, and bit lines. The bit lines laterally extend along a second horizontal direction. Each periodic two-dimensional array of memory openings includes…
