Plane programming scheme for non-volatile memory with large block sizes
Granted: October 17, 2023
Patent Number:
11789612
For a non-volatile memory system with a multi-plane memory die having a large block size, to be able to more readily accommodate zone-based host data using zones that are of a smaller size that the block size on the memory, the memory system assigns data from different zones to different subsets of the planes of a common memory die. The memory system is configured to accumulate the data from the different zones into different write queues and then assemble the data from the different…
State dependent VPVD voltages for more uniform threshold voltage distributions in a memory device
Granted: October 17, 2023
Patent Number:
11790992
The storage device includes a non-volatile memory with control circuitry and an array of memory cells that are arranged in a plurality of word lines. The control circuitry is configured to program the memory cells in a plurality of programming loops which include applying a programming pulse to a selected word line to program at least one memory cell of the selected word line to a programmed data state. The programming loops also include simultaneously applying a verify pulse to the…
Non-volatile memory with updating of read compare voltages based on measured current
Granted: October 17, 2023
Patent Number:
11791001
A memory system reads data from non-volatile memory cells using a set of read compare voltages to determine which data state the memory cells are in, where each data state is associated with predetermined data values. The read compare voltages are determined dynamically based on a difference between memory cell current at time of programming and memory cell current at time of reading.
Three-dimensional memory device having support-die-assisted source power distribution and method of making thereof
Granted: October 17, 2023
Patent Number:
11791327
A memory-containing die includes a three-dimensional memory array, a memory dielectric material layer located on a first side of the three-dimensional memory array, and memory-side bonding pads. A logic die includes a peripheral circuitry configured to control operation of the three-dimensional memory array, logic dielectric material layers located on a first side of the peripheral circuitry, and logic-side bonding pads included in the logic dielectric material layers. The logic-side…
Dual sacrificial material replacement process for a three-dimensional memory device and structure formed by the same
Granted: October 17, 2023
Patent Number:
11792986
A vertical repetition of a unit layer stack includes an insulating layer, a first sacrificial material layer, another insulating layer, and a second sacrificial material layer. A memory opening is formed through the vertical repetition, and a memory opening fill structure is formed in the memory opening. A backside trench is formed through the alternating stack. The first sacrificial material layers are replaced with first electrically conductive layers, and the second sacrificial…
Three-dimensional memory device with separated contact regions and methods for forming the same
Granted: October 17, 2023
Patent Number:
11792988
A memory die includes an alternating stack of insulating layers and electrically conductive layers through which memory opening fill structures vertically extend. The memory die includes at least three memory array regions interlaced with at least two contact regions, or at least three contact regions interlaced with at least two memory array regions in the same memory plane. A logic die including at least two word line driver regions can be bonded to the memory die. The interlacing of…
Power off recovery in cross-point memory with threshold switching selectors
Granted: October 10, 2023
Patent Number:
11783895
In a memory array with a cross-point structure, at each cross-point junction a programmable resistive memory element, such as an MRAM memory cell, is connected in series with a threshold switching selector, such as an ovonic threshold switch. The threshold switching selector switches to a conducting state when a voltage above a threshold voltage is applied. When powered down for extended periods, the threshold voltage can drift upward. If the drift is excessive, this can make the memory…
Proactive edge word line leak detection for memory apparatus with on-pitch semi-circle drain side select gate technology
Granted: October 10, 2023
Patent Number:
11783903
A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to one of a plurality of word lines and arranged in strings and configured to retain a threshold voltage. A control means is coupled to the plurality of word lines and the strings. The control means is configured to apply a primary predetermined voltage to a primary location of the memory apparatus following an erase operation of the memory cells while simultaneously applying a…
Three-dimensional memory device with punch-through-resistant word lines and methods for forming the same
Granted: October 3, 2023
Patent Number:
11778818
An alternating stack of insulating layers and electrically conductive layers, a retro-stepped dielectric material portion overlying stepped surfaces of the alternating stack, and memory stack structures extending through the alternating stack are formed over a substrate. A patterned etch mask layer including discrete openings is formed thereabove. Via cavities through an upper region of the retro-stepped dielectric material portion by performing a first anisotropic etch process. Metal…
Vertical compression scheme for compressed soft bit data in non-volatile memories with data latch groups
Granted: October 3, 2023
Patent Number:
11776589
For a non-volatile memory that uses hard bit and soft bit data in error correction operations, to reduce the amount of soft bit data that needs to be transferred from a memory to the controller and improve memory system performance, the soft bit data can be compressed before transfer. After the soft bit data is read and stored into the internal data latches associated with the sense amplifiers, it is compressed within these internal data latches. The compressed soft bit data can then be…
Systems and methods for adjusting threshold voltage distribution due to semi-circle SGD
Granted: October 3, 2023
Patent Number:
11776628
The following disclosure is directed to mitigating issues related to semi-circle drain side select gate (SC-SGD) memory holes in memory structures. When a memory hole is cut, the channel and the charge trap layer of the memory hole cut. Further, the outer dielectric layer (used to shield the channel and the charge trap layer) is cut and partially removed. When the selected SC-SGD is selected for an operation (e.g., programming), the channel and the charge trap layer are exposed to…
Data conversion with data path circuits for use in double sense amp architecture with fractional bit assignment in non-volatile memory structures
Granted: October 3, 2023
Patent Number:
11776640
A method for programming a non-volatile memory structure, comprises initiating a two-dimensional fractional number of bits-per-cell programming scheme of a plurality of memory cells, wherein the memory structure comprises: (1) a first memory array comprising a first population of memory cells and the associated peripheral circuitry disposed below the first population of cells, (2) a second memory array positioned above the first memory array and comprising a second population of memory…
Systems and methods for distributing programming speed among blocks with different program-erase cycle counts
Granted: October 3, 2023
Patent Number:
11776643
Non-volatile memory systems and method for managing P/E cycling is disclosed. Memory systems include multi-plane (e.g., 2-plane or 4-plane) programming operations in which new blocks within a plane replace faulty/bad blocks. Existing blocks, having undergone several P/E cycles more than the new block(s), require a lower programming voltage and are programmed using an adaptive (reduced) programming voltage. New block(s) require an additional voltage, and a delta voltage is added to the…
Semiconductor structure containing pre-polymerized protective layer and method of making thereof
Granted: October 3, 2023
Patent Number:
11776922
A method of forming a semiconductor structure includes providing a semiconductor wafer including a plurality of semiconductor dies, providing a polymerized material layer, attaching the polymerized material layer to the semiconductor wafer such that the polymerized material layer is polymerized prior to the step of attaching the polymerized material layer to the semiconductor wafer, applying and patterning an etch mask layer over the polymerized material layer, such that openings are…
Three-dimensional memory device including III-V compound semiconductor channel layer and method of making the same
Granted: October 3, 2023
Patent Number:
11778817
A stack including a silicon oxide layer, a germanium-containing layer, and a III-V compound semiconductor layer is formed over a substrate. An alternating stack of insulating layers and spacer material layers is formed over the III-V compound semiconductor layer. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory openings are formed through the alternating stack and into the III-V compound semiconductor layer. Memory…
String based erase inhibit
Granted: September 26, 2023
Patent Number:
11769560
A non-volatile memory device, described herein, comprises: a plurality of memory strings and at least one control circuit in communication with the non-volatile memory cell array. The at least one control circuit is configured to perform, for the plurality of memory strings, one erase-verify iteration in an erase operation including determining whether at least one memory string of the plurality of memory strings passes an erase-verify test. The at least one control circuit is configured…
Time sequence data management
Granted: September 19, 2023
Patent Number:
11762817
Apparatuses, systems, and methods are disclosed for snapshots of a non-volatile device. A method includes writing data in a sequential log structure for a non-volatile device. A method includes marking a point, in a sequential log structure, for a snapshot of data. A method includes preserving a logical-to-physical mapping for a snapshot based on a marked point and a temporal order for data in a sequential log structure.
Reverse VT-state operation and optimized BiCS device structure
Granted: September 19, 2023
Patent Number:
11763907
Systems and methods for improving the reliability of non-volatile memory by reducing the number of memory cell transistors that experience excessive hole injection are described. The excessive hole injection may occur when the threshold voltage for a memory cell transistor is being set below a particular negative threshold voltage. To reduce the number of memory cell transistors with threshold voltages less than the particular negative threshold voltage, the programmed data states of the…
Non-volatile memory with sub-block based self-boosting scheme
Granted: June 27, 2023
Patent Number:
11688469
To help reduce program disturbs in non-selected NAND strings of a non-volatile memory, a sub-block based boosting scheme in introduced. For a three dimensional NAND memory structure, in which the memory cells above a joint region form an upper sub-block and memory cells below the joint region form a lower sub-block, dummy word lines in the joint region act as select gates to allow boosting at the sub-block level when the lower block is being programmed in a reverse order.
Forced current access with voltage clamping in cross-point array
Granted: June 27, 2023
Patent Number:
11688446
Technology for limiting a voltage difference between two selected conductive lines in a cross-point array when using a forced current approach is disclosed. In one aspect, the selected word line voltage is clamped to a voltage limit while driving an access current through a region of the selected word line and through a region of the selected bit line. The access current flows through the memory cell to allow a sufficient voltage to successfully read or write the memory cell, while not…
