Forced current access with voltage clamping in cross-point array
Granted: June 20, 2023
Patent Number:
11682442
Technology for limiting a voltage difference between two selected conductive lines in a cross-point array when using a forced current approach is disclosed. In one aspect, the selected word line voltage is clamped to a voltage limit while driving an access current through a region of the selected word line and through a region of the selected bit line. The access current flows through the memory cell to allow a sufficient voltage to successfully read or write the memory cell, while not…
Bonded three-dimensional memory devices with backside source power supply mesh and methods of making the same
Granted: June 13, 2023
Patent Number:
11676954
A semiconductor structure includes a memory die bonded to a logic die. The memory die includes an alternating stack of insulating layers and electrically conductive layers; memory openings extending through the alternating stack, memory opening fill structures located in the memory openings and comprising a respective vertical semiconductor channel and a respective memory film, a source layer contacting the vertical semiconductor channels, a backside isolation dielectric layer contacting…
Two-sided adjacent memory cell interference mitigation
Granted: June 6, 2023
Patent Number:
11670380
Technology for two-sided adjacent memory cell interference mitigation in a non-volatile storage system is disclosed. During reading of target memory cells, the storage system applies a suitable magnitude read pass voltage to a first unselected word line adjacent to a target word line to compensate for interference from adjacent cells on the first unselected word line while applying a suitable magnitude read reference voltage to the target word line to compensate for interference from…
Apparatus, system, and method for trimming analog temperature sensors
Granted: June 6, 2023
Patent Number:
11668612
A method for trimming analog temperature sensors. First, raise a temperature of a temperature sensor to a highest temperature of a qualification temperature range. Then, trim the temperature sensor such that a high temperature code generated by the temperature sensor represents an actual temperature reported by the temperature sensor at the highest temperature. Next, lower the temperature of the temperature sensor to a lowest temperature of the qualification temperature range. Determine…
Sub-block programming mode with multi-tier block
Granted: May 30, 2023
Patent Number:
11664075
Apparatuses and techniques are described for programming a multi-tier block in which sub-blocks are arranged in respective tiers. When a program operation involves the source-side sub-block, the NAND strings are pre-charged from the source line. When a program operation involves the drain-side sub-block, the NAND strings are pre-charged from the bit line. When a program operation involves an interior sub-block, the NAND strings can be pre-charged from the bit line if all sub-blocks on…
Compute-in-memory deep neural network inference engine using low-rank approximation technique
Granted: May 30, 2023
Patent Number:
11663471
Non-volatile memory structures for performing compute in memory inferencing for neural networks are presented. To improve performance, both in terms of speed and energy consumption, weight matrices are replaced with their singular value decomposition (SVD) and use of a low rank approximations (LRAs). The decomposition matrices can be stored in a single array, with the resultant LRA matrices requiring fewer weight values to be stored. The reduced sizes of the LRA matrices allow for…
Three-dimensional memory device including discrete charge storage elements and methods of forming the same
Granted: May 23, 2023
Patent Number:
11659711
An alternating stack of disposable material layers and silicon nitride layers is formed over a substrate. Memory openings are formed through the alternating stack, and memory opening fill structures are formed in the memory openings, wherein each of the memory opening fill structures comprises a charge storage material layer, a tunneling dielectric layer, and a vertical semiconductor channel Laterally-extending cavities are formed by removing the disposable material layers selective to…
Non-volatile memory with efficient testing during erase
Granted: May 23, 2023
Patent Number:
11657884
A non-volatile memory system erasing groups of connected memory cells separately performs erase verify for memory cells connected to even word lines to generate even results and erase verify for memory cells connected to odd word lines to generate odd results. The even results and the odd results are used to determine if the erase verify process indicates that the erasing has successful completed. In addition, for each group of connected memory cells, a last even result for the group is…
Kernel transformation techniques to reduce power consumption of binary input, binary weight in-memory convolutional neural network inference engine
Granted: May 23, 2023
Patent Number:
11657259
Techniques are presented for performing in-memory matrix multiplication operations for binary input, binary weight valued convolution neural network (CNN) inferencing. The weights of a filter are stored in pairs of memory cells of a storage class memory device, such as a ReRAM or phase change memory based devices. To reduce current consumption, the binary valued filters are transformed into ternary valued filters by taking sums and differences of binary valued filter pairs. The zero…
Sense amplifier mapping and control scheme for non-volatile memory
Granted: May 16, 2023
Patent Number:
11651800
A data storage includes a memory array including a plurality of memory cells, and peripheral circuitry disposed underneath the memory array. The peripheral circuitry includes an M-tier sense amplifier (SA) circuit including X stacks of SA latches, wherein each SA latch is respectively coupled to a bit line of a memory cell of the plurality of memory cells; and an N-tier memory cache data (XDL) circuit including Y stacks of XDL latches, wherein M is less than N, and X is greater than Y.…
Bonded assembly containing low dielectric constant bonding dielectric material
Granted: May 9, 2023
Patent Number:
11646283
A first metal layer can be deposited over first dielectric material layers of a first substrate, and can be patterned into first bonding pads. A first low-k material layer can be formed over the first bonding pads. The first low-k material layer includes a low-k dielectric material such as a MOF dielectric material or organosilicate glass. A second semiconductor die including second bonding pads can be provided. The first bonding pads are bonded to the second bonding pads to form a…
Bonded semiconductor die assembly with metal alloy bonding pads and methods of forming the same
Granted: May 9, 2023
Patent Number:
11646282
A bonded assembly includes a first semiconductor die and a second semiconductor die. The first semiconductor die includes first metallic bonding pads embedded in first dielectric material layers, the second semiconductor die includes second metallic bonding pads embedded in second dielectric material layers, the first metallic bonding pads are bonded to a respective one of the second metallic bonding pads; and each of the first metallic bonding pads includes a corrosion barrier layer…
Toggle mode frequency optimization by dynamic ODT matching for non-volatile memory
Granted: May 9, 2023
Patent Number:
11646085
A data storage system includes a plurality of memory dies and interface circuitry, including a receiver configured to receive pulses of a read clock signal; an I/O contact pad coupled to the receiver via a signal path of an interface channel; and on-die-termination (ODT) circuitry coupled to the I/O contact pad and the receiver. The ODT circuitry includes a plurality of resistor pairs, each including a pull-up resistor selectively coupled to the signal path via a first switch, and a…
Reliability compensation for uneven NAND block degradation
Granted: May 9, 2023
Patent Number:
11646081
Technology is provided for extending the useful life of a block of memory cells by changing an operating parameter in a physical region of the block that is more susceptible to wear than other regions. Changing the operating parameter in the physical region extends the life of that region, which extends the life of the block. The operating parameter may be, for example, a program voltage step size or a storage capacity of the memory cells. For example, using a smaller program voltage…
Bonded assembly containing low dielectric constant bonding dielectric material
Granted: May 9, 2023
Patent Number:
11646283
A first metal layer can be deposited over first dielectric material layers of a first substrate, and can be patterned into first bonding pads. A first low-k material layer can be formed over the first bonding pads. The first low-k material layer includes a low-k dielectric material such as a MOF dielectric material or organosilicate glass. A second semiconductor die including second bonding pads can be provided. The first bonding pads are bonded to the second bonding pads to form a…
Bonded semiconductor die assembly with metal alloy bonding pads and methods of forming the same
Granted: May 9, 2023
Patent Number:
11646282
A bonded assembly includes a first semiconductor die and a second semiconductor die. The first semiconductor die includes first metallic bonding pads embedded in first dielectric material layers, the second semiconductor die includes second metallic bonding pads embedded in second dielectric material layers, the first metallic bonding pads are bonded to a respective one of the second metallic bonding pads; and each of the first metallic bonding pads includes a corrosion barrier layer…
Toggle mode frequency optimization by dynamic ODT matching for non-volatile memory
Granted: May 9, 2023
Patent Number:
11646085
A data storage system includes a plurality of memory dies and interface circuitry, including a receiver configured to receive pulses of a read clock signal; an I/O contact pad coupled to the receiver via a signal path of an interface channel; and on-die-termination (ODT) circuitry coupled to the I/O contact pad and the receiver. The ODT circuitry includes a plurality of resistor pairs, each including a pull-up resistor selectively coupled to the signal path via a first switch, and a…
Reliability compensation for uneven NAND block degradation
Granted: May 9, 2023
Patent Number:
11646081
Technology is provided for extending the useful life of a block of memory cells by changing an operating parameter in a physical region of the block that is more susceptible to wear than other regions. Changing the operating parameter in the physical region extends the life of that region, which extends the life of the block. The operating parameter may be, for example, a program voltage step size or a storage capacity of the memory cells. For example, using a smaller program voltage…
Three-dimensional memory device with peripheral circuit located over support pillar array and method of making thereof
Granted: May 2, 2023
Patent Number:
11641746
A three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a substrate, memory stack structures extending through the first alternating stack, a second alternating stack of second insulating layers and second electrically conductive layers located over the substrate and laterally spaced from the first alternating stack, a contact-level dielectric layer overlying the first alternating stack and the…
Three-dimensional memory device containing self-aligned lateral contact elements and methods for forming the same
Granted: April 25, 2023
Patent Number:
11637038
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers having stepped surfaces, memory stack structures extending through the alternating stack, a retro-stepped dielectric material portion overlying the stepped surfaces, and pillar-shaped contact-opening assemblies located within a respective pillar-shaped volume vertically extending through the retro-stepped dielectric material portion and a region of the alternating stack…
