Apparatus and methods for smart verify with neighbor plane disturb detection
Granted: December 27, 2022
Patent Number:
11538538
An apparatus is provided that includes a plurality of non-volatile memory cells and a control circuit coupled to the non-volatile memory cells. The control circuit is configured to perform a first program-verify iteration on a first set of non-volatile memory cells coupled to a first word line to determine a first starting program voltage that programs the first set of the non-volatile memory cells to a first programmed state, and program a second set of non-volatile memory cells coupled…
Three-dimensional memory device containing bridges for enhanced structural support and methods of forming the same
Granted: December 20, 2022
Patent Number:
11532570
A three-dimensional memory device includes a first word-line region including a first alternating stack of first word lines and continuous insulating layers, first memory stack structures vertically extending through the first alternating stack, a second word-line region comprising a second alternating stack of second word lines and the continuous insulating layers, second memory stack structures vertically extending through the second alternating stack, plural dielectric separator…
Non-volatile memory with fast multi-level program verify
Granted: December 20, 2022
Patent Number:
11532370
To improve programming performance for a non-volatile memory , the verification of multiple programming levels can be performed based on a single discharge of a sensing capacitor through a selected memory cell by using different voltage levels on a second plate of the sensing capacitor: after discharging a first plate of the sensing capacitor through the selected memory cell, a result amount of charge is trapped on the first plate, which is then used to set first and second control gate…
Semiconductor structure containing multilayer bonding pads and methods of forming the same
Granted: December 13, 2022
Patent Number:
11527500
A bonded assembly includes a first semiconductor die that includes first semiconductor devices, and a first pad-level dielectric layer and embedding first bonding pads; and a second semiconductor die that includes second semiconductor devices, and a second pad-level dielectric layer embedding second bonding pads that includes a respective second pad base portion. Each of the first bonding pads includes a respective first pad base portion and a respective first metal alloy material…
Binary weighted voltage encoding scheme for supporting multi-bit input precision
Granted: December 6, 2022
Patent Number:
11521658
An illustrative embodiment disclosed herein is an apparatus including a non-volatile memory cell and multi-bit input circuitry that simultaneously receives a plurality of bits, receives a supply voltage, converts the plurality of bits and the supply voltage into a multiply voltage, and applies the multiply voltage to the non-volatile memory cell. The non-volatile memory cell may pass a memory cell current in response to the multiply voltage. A magnitude of the multiply voltage may…
Three-dimensional memory device containing low resistance source-level contact and method of making thereof
Granted: December 6, 2022
Patent Number:
11521984
A source-level sacrificial layer and an alternating stack of insulating layers and spacer material layers are formed over a substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory openings are formed through the alternating stack and the source-level sacrificial layer, and memory opening fill structures are formed. A source cavity is formed by removing the source-level sacrificial layer, and exposing an outer sidewall…
Triggering next state verify in program loop for nonvolatile memory
Granted: December 6, 2022
Patent Number:
11521691
Apparatus and methods are described to program memory cells and control bit line discharge schemes during programming based on the data pattern. The memory controller can predict program data pattern based on SLC pulse number and TLC data completion signals and use these signals to adjust when the inhibited bit lines can discharge. Once a TLC program operation have more one data, the memory controller will enable EQVDDSA_PROG to equalize to VDDSA, and then discharge. In SLC program, the…
Memory apparatus and method of operation using state bit-scan dependent ramp rate for peak current reduction during program operation
Granted: December 6, 2022
Patent Number:
11521686
A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines and bit lines and configured to retain a threshold voltage corresponding to one of a plurality of data states following a program operation. A control circuit is coupled to the word lines and the bit lines. The control circuit is configured to count a bit-scan quantity of the memory cells during a bit-scan of the program operation. The control circuit determines whether the…
Memory apparatus and method of operation using negative kick clamp for fast read
Granted: December 6, 2022
Patent Number:
11521677
A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and arranged in strings and configured to retain a threshold voltage. A control circuit is coupled to the word lines and strings and is configured to compute a target word line voltage including a kicking voltage to be applied to selected ones of word lines for a kick time during a read operation. The control circuit extends the kick time by a compensation time to a…
Block-dependent cell source bounce impact reduction in non-volatile memory
Granted: December 6, 2022
Patent Number:
11521675
A data storage system includes a storage medium coupled to a storage controller via an electrical interface connected to a plurality of input/output (IO) pads of the storage medium. The storage medium receives a read or write instruction from the storage controller via the IO pads, associates the read or write instruction with memory cells of a first block of a first plane of a plurality of planes of the storage medium, and adjusts a word line voltage level or a source line voltage level…
Multi-resistance MRAM
Granted: November 29, 2022
Patent Number:
11515472
Apparatuses, systems, and methods are disclosed for magnetoresistive random access memory. A magnetic tunnel junction (MTJ) for storing data may include a reference layer. A free layer of an MTJ may be separated from a reference layer by a barrier layer. A free layer may be configured such that one or more resistance states for an MTJ correspond to one or more positions of a magnetic domain wall within the free layer. A domain stabilization layer may be coupled to a portion of a free…
Three-dimensional memory device including laterally-undulating memory material layers and methods for forming the same
Granted: November 29, 2022
Patent Number:
11515326
A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel and a memory material layer. A vertical stack of insulating material portions can be provided at levels of the insulating layers to provide a laterally-undulating profile to the…
Three-dimensional memory device including through-memory-level via structures and methods of making the same
Granted: November 29, 2022
Patent Number:
11515317
A three-dimensional memory device can include at least one alternating stack of insulating layers and electrically conductive layers located over a semiconductor material layer, memory stack structures vertically extending through the at least one alternating stack, and a vertical stack of dielectric plates interlaced with laterally extending portions of the insulating layers of the at least one alternating stack. A conductive via structure can vertically extend through each dielectric…
Bonded assembly containing oxidation barriers, hybrid bonding, or air gap, and methods of forming the same
Granted: November 29, 2022
Patent Number:
11515273
At least one polymer material may be employed to facilitate bonding between the semiconductor dies. Plasma treatment, formation of a blended polymer, or formation of polymer hairs may be employed to enhance bonding. Alternatively, air gaps can be formed by subsequently removing the polymer material to reduce capacitive coupling between adjacent bonding pads.
Three dimensional semiconductor device containing composite contact via structures and methods of making the same
Granted: November 29, 2022
Patent Number:
11515250
A semiconductor structure includes at least one first semiconductor device located on a substrate, lower-level dielectric material layers embedding lower-level metal interconnect structures, at least one second semiconductor device and a dielectric material portion that overlie the lower-level dielectric material layers, at least one upper-level dielectric material layer, and an interconnection via structure vertically extending from the at least one upper-level dielectric material layer…
Semiconductor die including edge ring structures and methods for making the same
Granted: November 29, 2022
Patent Number:
11515227
Semiconductor devices laterally surrounded by at least one dielectric material portion are formed over a substrate. At least one edge seal ring structure is formed around the semiconductor devices and the at least one dielectric material portion. One or more of the at least one edge seal ring structure has a horizontal cross-sectional profile that includes laterally-extending regions that extend laterally with a uniform width between an inner sidewall and an outer sidewall, and notch…
Program tail plane comparator for non-volatile memory structures
Granted: November 29, 2022
Patent Number:
11514991
A method for detecting and isolating defective memory plane(s) of a non-volatile memory structure during a program verify operation, comprising: initiating, for each plane, a word line verify voltage level scan with a bit scan pass fail criterion and at a starting voltage located within an intended program threshold voltage distribution curve, incrementally decreasing the word line verify voltage by a predetermined offset until a specific condition of the scan is obtained, and storing…
Two way single VREF trim for fully differential CDAC for accurate temperature sensing
Granted: November 29, 2022
Patent Number:
11514990
A temperature sensing circuit of a data storage system includes a temperature sensor, a digital-to-analog circuit, and a reference generation and trimming circuit configured to generate a common mode voltage (VCM), a positive reference voltage (VREFP), and a negative reference voltage (VREFN) using a single band gap reference signal. The trimming circuit is configured to trim the VCM, VREFP, and VREFN by adjusting a VC trim signal to increase the VCM until a VCM error is below a…
Pre-computation of memory core control signals
Granted: November 22, 2022
Patent Number:
11507498
An apparatus including a memory structure comprising non-volatile memory cells and a microcontroller. The microcontroller is configured to output Core Timing Control (CTC) signals that are used to control voltages applied in the memory structure. In one aspect, information from which the CTC signals may be generated is pre-computed and stored. This pre-computation may be performed in a power on phase of the memory system. When a request to perform a memory operation is received, the…
Non-volatile memory with capacitors using metal under signal line or above a device capacitor
Granted: November 22, 2022
Patent Number:
11508654
A non-volatile storage apparatus comprises a non-volatile memory structure and a plurality of I/O pads in communication with the non-volatile memory structure. The I/O pads include a power I/O pad, a ground I/O pad and data/control I/O pads. The non-volatile storage apparatus further comprises one or more capacitors connected to the power I/O pad and the ground I/O pad. The one or more capacitors are positioned in one or more metal interconnect layers below the signal lines and/or above…
