Bonded three-dimensional memory devices and methods of making the same by replacing carrier substrate with source layer
Granted: November 22, 2022
Patent Number:
11508711
A memory die includes an alternating stack of insulating layers and electrically conductive layers, memory stack structures extending through the alternating stack, and each of the memory stack structures includes a respective vertical semiconductor channel and a respective memory film, drain regions located at a first end of a respective one of the vertical semiconductor channels, and a source layer having a first surface and a second surface. The first surface is located at a second…
Non-volatile memory with capacitors using metal under signal line or above a device capacitor
Granted: November 22, 2022
Patent Number:
11508654
A non-volatile storage apparatus comprises a non-volatile memory structure and a plurality of I/O pads in communication with the non-volatile memory structure. The I/O pads include a power I/O pad, a ground I/O pad and data/control I/O pads. The non-volatile storage apparatus further comprises one or more capacitors connected to the power I/O pad and the ground I/O pad. The one or more capacitors are positioned in one or more metal interconnect layers below the signal lines and/or above…
Periodic write to improve data retention
Granted: November 22, 2022
Patent Number:
11508440
A nonvolatile memory control method includes a step of writing, repeatedly to a nonvolatile memory cells. The method continues with detecting when writing reaches a writing threshold value. Upon reaching the writing threshold, the method continues with driving a charge to at least one parasitic area intermediate at least two charge storage areas of the nonvolatile memory cells to improve data retention in at least one of the at least two charge storage areas of the nonvolatile memory…
Pre-computation of memory core control signals
Granted: November 22, 2022
Patent Number:
11507498
An apparatus including a memory structure comprising non-volatile memory cells and a microcontroller. The microcontroller is configured to output Core Timing Control (CTC) signals that are used to control voltages applied in the memory structure. In one aspect, information from which the CTC signals may be generated is pre-computed and stored. This pre-computation may be performed in a power on phase of the memory system. When a request to perform a memory operation is received, the…
Antiferroelectric memory devices and methods of making the same
Granted: November 15, 2022
Patent Number:
11502104
An antiferroelectric memory device includes at least one antiferroelectric memory cell. Each of the at least one antiferroelectric memory cell includes a first electrode, a second electrode and a stack containing an antiferroelectric layer and a doped semiconductor layer or a ferroelectric layer located between the first and the second electrodes.
Read operation or word line voltage refresh operation in memory device with reduced peak current
Granted: November 15, 2022
Patent Number:
11501837
A reducing peak current consumption in a memory device when performing a word line voltage refresh operation or a read operation. When a word line voltage refresh operation or read operation is performed for the first time after a memory device powers up, the operation is performed with a power-saving technique such as reducing a ramp up rate of a voltage pulse, ramping up the voltage pulse in multiple steps, initiating the ramp up for different groups of word lines in a block at…
Three-dimensional memory device and method of erasing thereof from a source side
Granted: November 15, 2022
Patent Number:
11501835
A method of erasing vertical NAND strings from a source side of the vertical NAND strings includes applying a relatively high erase voltage to a source line, applying a relatively low voltage or 0 V to bit lines, applying a first drain-select-level voltage that is less than the erase voltage to one of the first drain-select-level electrically conductive layers, and applying a second drain-select-level voltage that is greater than the first drain-select-level voltage and not greater than…
Power off recovery in cross-point memory with threshold switching selectors
Granted: November 15, 2022
Patent Number:
11501831
In a memory array with a cross-point structure, at each cross-point junction a programmable resistive memory element, such as an MRAM memory cell, is connected in series with a threshold switching selector, such as an ovonic threshold switch. The threshold switching selector switches to a conducting state when a voltage above a threshold voltage is applied. When powered down for extended periods, the threshold voltage can drift upward. If the drift is excessive, this can make the memory…
Three-dimensional memory device containing a shared word line driver across different tiers and methods for making the same
Granted: November 15, 2022
Patent Number:
11501821
A semiconductor structure includes a peripheral circuit, a first three-dimensional memory array overlying the peripheral circuit and including a first alternating stack of first insulating layers and first electrically conductive layers containing first word lines and first select lines, and first memory stack structures vertically extending through the first alternating stack, and a second three-dimensional memory array overlying the first three-dimensional memory array and including a…
Multi-tier three-dimensional memory device with dielectric support pillars and methods for making the same
Granted: November 8, 2022
Patent Number:
11495616
A semiconductor device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate including a semiconductor material layer, a memory opening and a support opening extending through the alternating stack, a memory opening fill structure located in the memory opening and including a memory film and a semiconductor material portion in contact with the semiconductor material layer, and a support pillar structure located in the support…
Three-dimensional memory device with high mobility channels and nickel aluminum silicide or germanide drain contacts and method of making the same
Granted: November 8, 2022
Patent Number:
11495613
A memory device can include a strained single-crystalline silicon layer and an alternating stack of insulating layers and electrically conductive layers located over the strained single-crystalline silicon layer. A memory opening fill structure extending through the alternating stack may include an epitaxial silicon-containing pedestal channel portion, and a vertical semiconductor channel, and a vertical stack of memory elements located adjacent to the vertical semiconductor channel…
Three-dimensional memory device including stairless word line contact structures for and method of making the same
Granted: November 8, 2022
Patent Number:
11495612
An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings and support openings are formed through the alternating stack, and memory opening fill structures and support pillar structures are formed in the memory openings and in the support openings, respectively. Via cavities extending to each of the sacrificial material layers are formed through the alternating stack without forming any stepped surfaces in the alternating stack.…
Non-volatile memory with erase verify skip
Granted: November 8, 2022
Patent Number:
11495311
A non-volatile storage apparatus is configured to perform erase verify during an erase process in order to account for differences in erase speed. In order to reduce the time used to perform the erase process (which includes the erase verify), the erase verify operation is skipped for certain memory cells based on a system parameter. For example, when erasing a block of memory cells, a series of erase voltage pulses are applied to the NAND strings in outer sub-blocks and inner sub-blocks…
Systems and methods for defining memory sub-blocks
Granted: November 1, 2022
Patent Number:
11487454
A method for memory block management includes identifying a first group of bit lines corresponding to memory blocks of a 3-dimensional memory array. The method also includes biasing the first group of bit lines to a first voltage using respective bit line biasing transistors. The method also includes identifying, for each memory block, respective sub-memory blocks corresponding to word lines of each memory block that intersect the first group of bit lines. The method also includes…
Three-dimensional memory device employing thinned insulating layers and methods for forming the same
Granted: November 1, 2022
Patent Number:
11489043
A three-dimensional memory device includes an alternating stack of word lines and at least one insulating layers or air gaps located over a substrate, a memory opening fill structure extending through the alternating stack. The memory opening fill structure includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. The word lines are thicker than the insulating layers or air gaps.
Multi-tier three-dimensional memory device with nested contact via structures and methods for forming the same
Granted: November 1, 2022
Patent Number:
11488975
A semiconductor structure includes a first alternating stack of first insulating layers and first electrically conductive layers having first stepped surfaces and located over a substrate, a second alternating stack of second insulating layers and second electrically conductive layers having second stepped surfaces, and memory opening fill structures extending through the alternating stacks. A contact via assembly is provided, which includes a first conductive via structure vertically…
Calibration for integrated memory assembly
Granted: November 1, 2022
Patent Number:
11488682
An integrated memory assembly comprises a memory die and a control die bonded to the memory die. The memory die includes a memory structure of non-volatile memory cells. The control die is configured to program user data to and read user data from the memory die based on one or more operational parameters. The control die is configured to calibrate the one or more operational parameters for the memory die. The control die is also configured to perform testing of the memory die using the…
Three-valued programming mechanism for non-volatile memory structures
Granted: November 1, 2022
Patent Number:
11488669
A method for programming three page user data in a memory array of a non-volatile memory system, comprising converting each three-bit value data pattern of the user data into a representative pair of two-bit data values, simultaneously programming two single-state memory cells with a first of the pair of representative two-bit data values, wherein the two single-state memory cells are located along a first common word line of two memory cell strings, and simultaneously programming two…
Concurrent multi-bit access in cross-point array
Granted: November 1, 2022
Patent Number:
11488662
Concurrent access of multiple memory cells in a cross-point memory array is disclosed. In one aspect, a forced current approach is used in which, while a select voltage is applied to a selected bit line, an access current is driven separately through each selected word line to concurrently drive the access current separately through each selected memory cell. Hence, multiple memory cells are concurrently accessed. In some aspects, the memory cells are accessed using a self-referenced…
Dynamic re-evaluation of parameters for non-volatile memory using microcontroller
Granted: November 1, 2022
Patent Number:
11487548
A non-volatile memory apparatus and corresponding method of operation are provided. The apparatus includes non-volatile memory cells in an integrated circuit device along with a microcontroller in communication with the non-volatile memory cells. The microcontroller is configured to receive a memory operation command and in response, determine a condition value of one of a plurality of conditions associated with the memory operation command and whether the one of the plurality of…
