Semiconductor die containing dummy metallic pads and methods of forming the same
Granted: May 3, 2022
Patent Number:
11322466
A first semiconductor die includes first semiconductor devices located over a first substrate, first interconnect-level dielectric layers embedding first metal interconnect structures and located over the first semiconductor devices, a first pad-level dielectric layer embedding first bonding pads and located over the first interconnect-level dielectric layers, and first edge seal structures laterally surrounding the first semiconductor devices. Each of the first edge seal structures…
Three-dimensional memory device with dielectric wall support structures and method of forming the same
Granted: May 3, 2022
Patent Number:
11322440
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located between line trenches, a first memory array region and a second memory array region, and a pair of dielectric wall structures located between the first line trench and the second line trench and between the memory array regions. Each layer within the alternating stack continuously extends between the first memory array region and the second memory array region…
Enhanced multistate verify techniques in a memory device
Granted: May 3, 2022
Patent Number:
11322213
A method comprises determining a verify voltage for a next iteration of a verify operation to be performed on memory cells a first set of memory cells of a selected word line, and determining data states for a second set of memory cells of at least one neighboring word line. The method further comprises determining, based on the data states, a verify voltage configuration that includes bit line voltage biases or sense times, and performing the next iteration of the verify operation on…
Dynamic tier selection for program verify in nonvolatile memory
Granted: April 26, 2022
Patent Number:
11315648
An apparatus includes a memory controller configured to apply selected one or ones of the program verify voltage levels to a single tier of memory cells. A memory controller is configured to: program data into the plurality of memory cells; and perform a program verify operation across multiple voltage levels with a first voltage level of the program verify operation being applied to a single tier that represents all of the tiers in the memory group and a second voltage level of the…
Word line discharge skip for faster read time
Granted: April 19, 2022
Patent Number:
11309030
Methods for improving read time performance and energy consumption when reading multiple pages within a memory block by dynamically skipping or accelerating unselected word line discharge cycles are described. In some cases, a controller or one or more control circuits in communication with word lines and bit lines associated with a memory block may detect that a read command or instruction for reading a second page within the memory block has arrived prior to the word line discharge…
Spin transfer torque MRAM with a spin torque oscillator stack and methods of making the same
Granted: April 19, 2022
Patent Number:
11309487
A MRAM cell includes a magnetic tunnel junction containing a reference layer having a fixed magnetization direction, a free layer, and a nonmagnetic tunnel barrier layer located between the reference layer and the free layer, a spin torque oscillator stack, and a first nonmagnetic spacer layer located between the free layer and the spin torque oscillator stack.
Semiconductor device containing tubular liner spacer for lateral confinement of self-aligned silicide portions and methods of forming the same
Granted: April 19, 2022
Patent Number:
11309402
A semiconductor structure includes a semiconductor channel of a first conductivity type located between a first and second active regions having a doping of a second conductivity type that is opposite of the first conductivity type, a gate stack structure that overlies the semiconductor channel, and includes a gate dielectric and a gate electrode, a first metal-semiconductor alloy portion embedded in the first active region, and a first composite contact via structure in contact with the…
Three-dimensional memory device containing ferroelectric memory elements encapsulated by transition metal-containing conductive elements and method of making thereof
Granted: April 19, 2022
Patent Number:
11309332
A three-dimensional ferroelectric memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, where each of the electrically conductive layers contains a transition metal element-containing conductive liner and a conductive fill material portion, a vertical semiconductor channel extending vertically through the alternating stack, a vertical stack of tubular transition metal element-containing conductive spacers laterally…
Three-dimensional NOR-type memory device and method of making the same
Granted: April 19, 2022
Patent Number:
11309329
A NOR-type three-dimensional memory device includes a vertically alternating stack of insulating layers and electrically conductive layers located over a substrate, and laterally alternating sequences of respective active region pillars and respective memory stack structures. Each laterally alternating sequence is electrically isolated from the electrically conductive layers by a respective blocking dielectric layer at each level of the electrically conductive layers. Each memory stack…
Stacked die assembly including double-sided inter-die bonding connections and methods of forming the same
Granted: April 19, 2022
Patent Number:
11309301
Multiple bonded units are provided, each of which includes a respective front-side die and a backside die. The two dies in each bonded unit may be a memory die and a logic die configured to control operation of memory elements in the memory die. Alternatively, the two dies may be memory dies. The multiple bonded units can be attached such that front-side external bonding pads have physically exposed surfaces that face upward and backside external bonding pads of each bonded unit have…
Three-dimensional memory device including ferroelectric-metal-insulator memory cells and methods of making the same
Granted: April 12, 2022
Patent Number:
11302716
A memory opening or a line trench is formed through an alternating stack of insulating layers and sacrificial material layers. A memory opening fill structure or a memory stack assembly is formed, which includes a vertical stack of discrete intermediate metallic electrodes formed on sidewalls of the sacrificial material layers, a gate dielectric layer, and a vertical semiconductor channel. Backside recesses are formed by removing the sacrificial material layers selective to the…
Three-dimensional memory device including a composite semiconductor channel and a horizontal source contact layer and method of making the same
Granted: April 12, 2022
Patent Number:
11302714
A three-dimensional memory device includes a source contact layer overlying a substrate, an alternating stack of insulating layers and electrically conductive layers located overlying the source contact layer, and a memory opening fill structure located within a memory opening extending through the alternating stack and the source contact layer. The memory opening fill structure includes a composite semiconductor channel and a memory film laterally surrounding the composite semiconductor…
Three-dimensional memory device including III-V compound semiconductor channel layer and method of making the same
Granted: April 12, 2022
Patent Number:
11302713
A stack including a silicon oxide layer, a germanium-containing layer, and a III-V compound semiconductor layer is formed over a substrate. An alternating stack of insulating layers and spacer material layers is formed over the III-V compound semiconductor layer. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory openings are formed through the alternating stack and into the III-V compound semiconductor layer. Memory…
Programming techniques including an all string verify mode for single-level cells of a memory device
Granted: April 12, 2022
Patent Number:
11302409
A storage device is disclosed herein. The storage device comprises a block including a plurality of memory cells and a circuit coupled to the plurality of memory cells of the block. The circuit is configured to program memory cells of a plurality of strings of a word line of the block and verify, for a plurality of sets of the memory cells, a data state of a set of the memory cells, where each set of the plurality of sets of the memory cells includes a memory cell from each string of the…
Microcontroller architecture for non-volatile memory
Granted: April 12, 2022
Patent Number:
11301176
A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The control circuit includes a programmable and reprogrammable microcontroller. The microcontroller has a first processor that executes instructions to coordinate sequences of voltages applied to the memory structure by a first circuit in order to perform memory operations. The microcontroller has a second processor that executes second instructions to control a second…
Three-dimensional memory device with vertical field effect transistors and method of making thereof
Granted: April 5, 2022
Patent Number:
11296113
A semiconductor structure includes at least one set of vertical field effect transistors embedded within dielectric material layers overlying a substrate. Each vertical field effect transistor includes a bottom doped semiconductor electrode, a vertical transistor channel, a cylindrical gate dielectric, and a top doped semiconductor electrode. A three-dimensional NAND memory array can be provided over the first field effect transistors, and can be electrically connected to the vertical…
Multi-layer barrier for CMOS under array type memory device and method of making thereof
Granted: April 5, 2022
Patent Number:
11296112
A semiconductor structure includes a doped semiconductor material portion, a metal-semiconductor alloy portion contacting the doped semiconductor material portion, a device contact via structure in direct contact with the metal-semiconductor alloy portion, and at least one dielectric material layer laterally surrounding the device contact via structure. The device contact via structure includes a barrier stack and a conductive fill material portion. The barrier stack includes at least…
Three-dimensional memory device including an inter-tier etch stop layer and method of making the same
Granted: April 5, 2022
Patent Number:
11296101
A three-dimensional memory device includes a first-tier alternating stack of first insulating layers and first electrically conductive layers located over a substrate, an etch stop material layer located over the first-tier alternating stack, a second-tier alternating stack of second insulating layers and second electrically conductive layers located over the etch stop material layer, inter-tier memory openings vertically extending through the second-tier alternating stack, the etch stop…
Semiconductor device containing metal-organic framework inter-line insulator structures and methods of manufacturing the same
Granted: April 5, 2022
Patent Number:
11296028
A structure, such as a semiconductor device, includes metal line structures located over a substrate and laterally spaced apart from each other. Each of the metal line structures includes planar metallic liner including a first metal element and a metal line body portion includes a second metal element that is different from the first metal element. Metal-organic framework (MOF) material portions are located between neighboring pairs of the metal line structures and contain metal ions or…
Multi-level ultra-low power inference engine accelerator
Granted: March 29, 2022
Patent Number:
11289171
Non-volatile memory structures for performing compute-in-memory inferencing for neural networks are presented. A memory array is formed according to a crosspoint architecture with a memory cell at each crosspoint junction. The multi-levels memory cells (MLCs) are formed of multiple of ultra-thin dielectric layers separated by metallic layers, where programming of the memory cell is done by selectively breaking down one or more of the dielectric layers by selecting the write voltage…
