Three-dimensional memory array with dual-level peripheral circuits and methods for forming the same
Granted: January 21, 2025
Patent Number:
12207459
A bonded assembly includes a backside peripheral circuit, a memory die and a first logic die. The memory die includes a doped semiconductor material layer, a three-dimensional memory array, and memory-side metal interconnect structures and first memory-side bonding pads embedded in memory-side dielectric material layers. The first logic die includes a logic-side peripheral circuit including a first subset of logic devices configured to control operation of the three-dimensional memory…
Test controller enabling a snapshot restore and resume operation within a device under test
Granted: January 21, 2025
Patent Number:
12205660
Techniques are provided for capturing a processing state snapshot of a device under test (DUT) that enable a previous test run to be restored and resumed from the same point the snapshot was taken. The techniques enable restoring the snapshot into the same or a different device to resume a previous test run. In an illustrative example, a DUT is controlled by a Joint Test Action Group (JTAG) test controller to capture a Steady State Snapshot by controlling peripheral components of the DUT…
Systems and methods for retaining inflight data during a power loss event
Granted: January 21, 2025
Patent Number:
12205658
Memory devices, or memory systems, described herein may include a controller (e.g., SSD controller) and a NAND memory device for storing inflight data. When the power loss event occurs, a memory system maintains (i.e., not un-select) the existing memory block being programmed at the time of power loss. The existing program operation at the event of power loss can be suspended by controller. The inflight data can be re-sent by controller directly to NAND latches, when power loss event was…
Hybrid smart verify for QLC/TLC die
Granted: January 21, 2025
Patent Number:
12205657
Technology is disclosed herein for smart verify in a memory system that has a four bit per cell program mode (or X4 mode) and also a three bit per cell program mode (or X3 mode). The X3 mode uses a three-bit gray code that is based on a four-bit gray code of the X4 mode. The memory system skips verify of states in the X3 mode, while using a considerable portion of the programming logic from the X4 mode. In one X3 mode the memory system skips B-state verify while the number of memory…
MLC programming techniques in a memory device
Granted: January 21, 2025
Patent Number:
12205654
The memory device includes a plurality of memory cells which are arranged in an array. The memory device further includes a plurality of bit lines that are coupled with the memory cells and a controller. The controller is configured to program the memory cells from an erased data state to three programmed data states in a programming operation that includes three programming pulses and zero verify operations using different patterns to dictate the application of inhibit voltages to the…
Overwrite read methods for resistance switching memory devices
Granted: January 21, 2025
Patent Number:
12205640
A method is provided that includes reading a plurality of resistance-switching memory cells comprising a block of data, decoding the block of data using an error correction code decoder, and based on results of the decoding, selectively performing an overwrite-read process to read the block of data. The overwrite read process determines a change in resistance of the resistance-switching memory cells in response to a write pulse.
Data storage device with balanced background operations and method therefor
Granted: January 14, 2025
Patent Number:
12197323
In solid state memory devices, garbage collection can be a bottleneck in meeting stringent performance requirements of certain hosts that generate a relatively-large amount of data (e.g., hosts that generate video data). With such hosts, the performance drop caused by background garbage collection can result in video recording failures. The memory device and method presented herein performs background operations in such a way as to enhance sustained performance. In general, a counter is…
Three-dimensional memory device and method of making the same using differential thinning of vertical channels
Granted: January 14, 2025
Patent Number:
12200932
An alternating stack of insulating layers and spacer material layers is formed over a substrate. An insulating cap layer is formed thereupon. A memory opening is formed, which has a greater lateral dimension at a level of an upper insulating cap sublayer than at a level of a lower insulating cap sublayer. A memory film and a semiconductor channel material layer is formed in the memory opening. Ions of at least one dopant species is implanted into a top portion of the semiconductor…
Command and address sequencing in parallel with data operations
Granted: January 14, 2025
Patent Number:
12197783
A command/address sequence associated with a read/write operation for a memory device that utilizes an existing test data bus in a novel way that obviates the need to utilize an I/O bus for the command/address sequence. As such, the command/address sequence can be performed in parallel with the read/write operations, thereby removing a performance bottleneck that would otherwise be caused by the command and address sequencing. The command/address sequence detects a first enable signal…
Storage of control data information
Granted: January 14, 2025
Patent Number:
12197744
Methods for storing control information for memory operations within spare physical blocks. During formatting of a data storage device, spare memory blocks may be identified within memory dies and placed into a spare block pool. Upon initiation of a block exchange event for a control block, a controller determines whether a spare block is available in the spare block pool. When a spare block is available, data from the control block is copied to the spare block to generate a debug block.…
File system integration into data mining model
Granted: January 14, 2025
Patent Number:
12197318
Aspects of a storage device including a memory and a controller are provided. The controller may collect, by an association rule mining (ARM) model, file system data from a host file system, the file system data defining at least one attribute of a file. The controller may receive, from the host, a memory command associated with the file. The controller can associate, by the ARM model, the at least one attribute with the file. The controller may perform the memory command based on the…
Exception handling using security subsystem in storage device
Granted: January 14, 2025
Patent Number:
12197287
A data storage device includes a host interface for coupling the data storage device to a host system. The data storage device also includes a device memory for storing or providing data in response to commands receive from the host system. The data storage device also includes a controller comprising a storage subsystem and a security subsystem. The storage subsystem is configured to receive a host command from the host interface, and process the host command for the device memory. The…
Data storage device and method for using zones of memory in a read scrub operation
Granted: January 14, 2025
Patent Number:
12197284
A read to a wordline can cause a read disturb error on neighboring wordlines. Instead of scanning the entire memory to identify wordlines that have a read disturb problem, a localized read scan approach can be used. In this approach, the memory is organized into several zones, where each zone contains several wordlines. The number of reads in each zone is tracked, and, after a certain number of reads, the data in the zone is read. If the error rate of the data exceeds a threshold, the…
Low power state staging
Granted: January 7, 2025
Patent Number:
12189451
The present disclosure generally relates to split, non-operational power states for a data storage device. The data storage device can transition between the split, non-operational power states without advertising the transition to the host device. The power state parameters that are advertised to the host device are adjusted such that the host device is guided to the correct power decision based on the advertised power and duration. By splitting the non-operational power states, the…
Three-dimensional NAND memory device with reduced reverse dipole effect and method for forming the same
Granted: January 7, 2025
Patent Number:
12193228
A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening. The memory opening fill structure includes a memory film and a vertical semiconductor channel. The memory film includes a tunneling dielectric layer, a charge storage layer that laterally surrounds the tunneling dielectric…
Printed circuit board having a sacrificial pad to mitigate galvanic corrosion
Granted: January 7, 2025
Patent Number:
12193166
In one example, the present application describes a Printed Circuit Board (PCB) that mitigates galvanic corrosion during an Organic Solderability Preservative (OSP) process used during fabrication of the PCB. The PCB includes a first metal pattern and a second metal pattern electrically coupled to each other, where the first and second metal patterns are different metals. The first metal pattern has a first area that is exposed by a solder mask layer, and the second metal pattern has a…
PPA improvement for voltage mode driver and on-die termination (ODT)
Granted: January 7, 2025
Patent Number:
12191854
Systems and methods for improving the power, performance, and area (PPA) for a voltage mode driver and on die termination (ODT). A voltage mode driver having first and second circuits in a pulldown design. The first circuit has a plurality of nMOS devices in parallel, the plurality of nMOS devices being common to a first resistor. The second circuit is in parallel with the first circuit and has an nMOS device in series with a second resistor. The second circuit is configured to be…
Plane level dedicated starting program voltage to reduce program time for multi-plane concurrent program operation
Granted: January 7, 2025
Patent Number:
12190969
A memory apparatus and operating method are provided. The apparatus includes memory cells connected to word lines and disposed in memory holes and configured to retain a threshold voltage. The memory holes are organized in rows grouped in strings and the strings comprise a plurality of blocks which comprise planes. A control means is configured to program the memory cells connected to one of the word lines and associated with one of the strings in each of the plurality of planes and…
Optimized SSD for game loading and rendering
Granted: January 7, 2025
Patent Number:
12189956
Aspects are provided for optimizing game loading and rendering using an RMB dedicated for predicted host data that is accessible to a host and to a controller of a storage device. The controller obtains a bitmap indicating a status of a buffer in the RMB, receives from the host a read command indicating a logical address, predicts and reads from an NVM host data associated with a predicted logical address that is subsequent to the logical address, and loads the host data in the buffer in…
Data storage device and method for token generation and parameter anonymization
Granted: January 7, 2025
Patent Number:
12189818
A data storage device and method for token generation and parameter anonymization are provided. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to receive a plurality of tokens and data comprising a plurality of data portions, which each token identifies a different set of the data portions to anonymize; create a plurality of anonymized versions of the data per the plurality of tokens; and store each of the plurality…
