Word line layer dependent stress and screen voltage
Granted: February 18, 2025
Patent Number:
12230344
Technology is disclosed for testing a 3D memory structure. The 3D memory structure has blocks with layers of word lines. Each word line is connected to control gates of NAND memory cells. The 3D memory structure may be tested while concurrently applying a set of layer dependent voltages to a corresponding set of word lines. The magnitude of each layer dependent voltage may depend on which layer the word line to which the voltage is applied resides. There may be physical differences…
Data latch programming algorithm for multi-bit-per-cell memory devices
Granted: February 18, 2025
Patent Number:
12230335
A multi-stage method for programming an n-bit memory cell array using a fixed number of data latches is disclosed. The fixed number of data latches may be a reduced number of data latches in sense amplifier and data latch (SADL) peripheral circuitry than is required by existing programming techniques. As such, the die area taken up by the SADL circuitry can be reduced, which in turn, reduces overall chip area. The multi-stage programming method may include utilizing a first data latch to…
Read collision avoidance in sequential mixed workloads
Granted: February 18, 2025
Patent Number:
12229423
A data storage device processes a mixed workload including a plurality of superblocks to be written to and read from a plurality of memory dies, where each of the plurality of superblocks to be apportioned among the plurality of memory dies. The data storage device writes a first data stripe associated with a first superblock to the plurality of memory dies according to a sequential write pattern, and reads the first data stripe associated with the first superblock from the plurality of…
Hold-up capacitor failure handling in data storage devices
Granted: February 18, 2025
Patent Number:
12229416
A data storage device includes a plurality of hold-up capacitors configured to provide back-up power for a non-volatile memory, a controller, and a write cache. The controller is configured to detect one or more failed hold-up capacitors of the plurality of hold-up capacitors; and in response to detecting the one or more failed hold-up capacitors: perform one or more quiesce operations and determine a count of the one or more failed hold-up capacitors. Based on the count of the one or…
Hole channel pre-charge to enable large-volume in-place data sanitization of non-volatile memory
Granted: February 18, 2025
Patent Number:
12229415
In NAND memory, data sanitization allows a relatively small unit of data (e.g., less than a block) to be effectively destroyed by increasing threshold voltages of memory cells from their programmed threshold voltage to the highest threshold state. To reduce the amount of disturb on memory cells not selected for data sanitization, prior to applying a program voltage to a target word line, a hole based pre-charge operation is performed. More specifically, for NAND strings having a memory…
Hybrid logical to physical mapping for ZNS based SSDs
Granted: February 18, 2025
Patent Number:
12229403
Aspects of a storage device are provided that handle host commands associated with active and inactive zones using a hybrid L2P mapping system. The storage device includes a NVM, a controller, a first volatile memory and a second volatile memory. The controller allocates, as a superblock, one or more physical blocks respectively in one or more memory dies of the NVM, receives write commands including logical addresses associated with active zones, and stores in an L2P mapping table L2P…
Devices and methods for providing port matching features for USB-C cables and ports
Granted: February 18, 2025
Patent Number:
12229070
Systems and methods are disclosed for providing port matching features for storage devices and cables. In certain embodiments, a data storage device includes a non-volatile memory, a controller configured to process data storage requests, a plurality of ports associated with different protocols, wherein the plurality of ports have the same connector type, and each port includes a port matching feature indicative of a protocol associated with the port, and a plurality of cables associated…
Storage device for storing model checkpoints of recommendation deep-learning models
Granted: February 18, 2025
Patent Number:
12229016
The present disclosure generally relates to utilizing improved DL training models stored in non-volatile memory to optimize data transfer and storage. The proposed system would identify workloads of DNN training and occasionally check the difference rate between successive data transfers (representing successive training iterations of the model). Comparing the difference rate to given thresholds could indicate “recommendation-system” typical use case. In such a case the NAND…
Delayed XOR rebuild with priority in multi-protocol products
Granted: February 18, 2025
Patent Number:
12229008
A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to operate under at least a first device protocol and a second device protocol, where the first and second device protocols have different endurance and protection requirements. When data is programmed to the memory device using the first device protocol, but is read from the memory device using the second device protocol, the differing endurance and protection…
Voltage controlled magnetic anisotropy (VCMA) memory devices including platinum containing layer in contact with free layer
Granted: February 11, 2025
Patent Number:
12225828
A memory device includes a first electrode, a second electrode, and a magnetic tunnel junction located between the first electrode and the second electrode. The magnetic tunnel junction includes a reference layer, a free layer, a nonmagnetic tunnel barrier layer located between the reference layer and the free layer, and a platinum-containing layer containing platinum and at least one element selected from iridium, hafnium or ruthenium. The platinum-containing layer contacts the free…
Three-dimensional memory device with doped semiconductor bridge structures and methods for forming the same
Granted: February 11, 2025
Patent Number:
12225720
A vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate, and memory opening fill structures including vertical stacks of memory elements are formed through the vertically alternating sequence. Backside trenches are formed to divide the vertically alternating sequence into a plurality of alternating stacks of insulating layers and sacrificial material layers. Bridge structures are formed within each of the…
Authorization requests from a data storage device to multiple manager devices
Granted: February 11, 2025
Patent Number:
12225111
Disclosed herein is a data storage device. A data port transmits data between a host computer system and the data storage device. A non-volatile storage medium stores encrypted user content data and a cryptography engine connected between the data port and the storage medium uses a cryptographic key to decrypt the encrypted user content data. Multiple manager device records each comprise a first key identical for each of the records, and a second key that different for each of the…
Clamped semiconductor wafers and semiconductor devices
Granted: February 11, 2025
Patent Number:
12224259
Clamped semiconductor wafers and clamped semiconductor devices include reservoirs filled with a flowable metal which hardens to allow the wafers/devices to be shipped or stored. The hardened metal may also be reflowed to a liquid to allow clamping of the semiconductor wafers together and to allow clamping of the semiconductor packages together. The flowable metal may be filled into the reservoirs as a liquid or paste. Thereafter, the flowable metal may be cooled to harden the flowable…
Semiconductor wafer and semiconductor dies formed therefrom including grooves along long edges of the semiconductor dies
Granted: February 11, 2025
Patent Number:
12224248
A semiconductor wafer includes semiconductor dies and laser grooves formed in the scribe lines along the long edges of the semiconductor dies. A laser groove extends between the long edges of two adjacent semiconductor dies to encompass the corners of the two adjacent semiconductor dies. When diced, the resulting semiconductor dies have portions of the corners removed.
Devices and methods for genome sequencing
Granted: February 11, 2025
Patent Number:
12224042
A device includes arrays of Non-Volatile Memory (NVM) cells. Reference sequences representing portions of a genome are stored in respective groups of NVM cells. Exact matching phase substring sequences representing portions of at least one sample read are loaded into groups of NVM cells. One or more groups of NVM cells are identified where the stored reference sequence matches the loaded exact matching phase substring sequence using the arrays at Content Addressable Memories (CAMs).…
Multi-stage data compaction in NAND
Granted: February 11, 2025
Patent Number:
12224014
Technology is disclosed herein for multi-stage data compaction. In a first data compaction stage valid data fragments from source erase block(s) are programmed into a destination erase block at two bits per memory cell. In a second data compaction stage additional valid data from the source erase block(s) is programmed into the destination erase block at two bits per memory cell. In this second stage, the same physical pages of memory cells in the destination erase block may be…
Non-volatile memory with concurrent sub-block programming
Granted: February 11, 2025
Patent Number:
12224011
A non-volatile memory system includes a control circuit connected to non-volatile memory cells. The control circuit is configured to concurrently program memory cells connected to different word lines that are in different sub-blocks of different blocks in different planes of a die.
Data storage device and method for dynamic controller memory buffer allocation
Granted: February 11, 2025
Patent Number:
12223206
A data storage device and method for dynamic controller memory buffer allocation are disclosed. In one embodiment, a data storage device is provided comprising a memory and a controller with a controller memory buffer. The controller is configured to communicate with the non-volatile memory and is further configured to configure a size of the controller memory buffer; receive a request from the host to modify the size of the controller memory buffer during operation of the data storage…
Cache writing to zones to maximize write bandwidth
Granted: February 11, 2025
Patent Number:
12223175
Instead of having all zones open across all dies, optimizing caching of non-direct write active zones using a host append point (HAP) for maximum write bandwidth is sufficient. The controller will calculate the write rate for a jumbo device (JD). Based on the JD with lowest total write rate, the controller will assign the JD a new zone. The controller will then determine whether the write rate is either appropriate for a cache write or for a direct write. Based on the determination, the…
ZQ calibration circuit and method for memory interfaces
Granted: February 4, 2025
Patent Number:
12216596
Systems and methods disclosed herein provide for an improved termination leg unit design and method of trimming impedance thereof, which provides for improved impedance matching for process variations, along with variations in temperature and voltage. Example implementation provide for a leg unit circuit design that includes a first circuit compensating for temperature and voltage variations and a second circuit, connected in series with the first circuit, compensating for process…
