Authentication of sanitize erase
Granted: December 24, 2024
Patent Number:
12175114
Adding a bypass module and a pattern detector module to a data path of a controller will increase the efficiency of both sanitize block erase audit and sanitize crypto erase audit operations. The sanitize crypto erase audit skips an end to end (E2E) protection module to provide decrypted data to a static random access memory (SRAM) buffer and ultimately a host device through a direct memory access (DMA) module. The sanitize block erase audit utilizes the pattern detector module to…
Optimization of an active range of mSets stored in a compressed address table
Granted: December 24, 2024
Patent Number:
12174736
A controller maintains logical block address (LBA) to physical block address (PBA) mappings as mSets in a storage address table (SAT). Because the SAT may include many mappings, and, consequently, have a large size, the SAT may be stored in a distanced memory from the controller, such as a non-volatile memory device of the data storage device or a host memory buffer of a host device that is coupled to the data storage device. In order to optimize performance, a portion of the SAT may be…
Partial speed changes to improve in-order transfer
Granted: December 10, 2024
Patent Number:
12166505
A data storage device with partial speed changes to improve in-order data transfer. Rather than determining an ECC decoder on a first available decoder basis, the ECC decoder may be based on the ECC decoder level. A memory device will have at least one FMU that has a syndrome weight (SW). The disclosure proposes assigning FMU's based on the SW rate. At the time the command is read, the data storage device determines which level of decoder will be assigned to the FMU. The determination…
Data storage with improved cache read
Granted: December 10, 2024
Patent Number:
12165735
The present disclosure generally relates to optimizing memory storage performance and power usage. Read operations from flash memory are comprised of a sense operation and a read transfer operation. Usually, these two operations are performed in parallel to achieve high read performance. However, these two operations typically do not take the same amount of time, leading to inefficiencies. By measuring sense busy time, the read transfer clock may be set accordingly so the two operations…
Speculative command processing interface in storage systems
Granted: December 10, 2024
Patent Number:
12164807
Systems and methods are disclosed for providing speculative command processing. In certain embodiments, a data storage device includes a non-volatile memory, a buffer, and a controller configured to: receive one or more actual requests for data from one or more hosts, wherein an actual request is associated with data confirmed to be required by an application on a host; receive one or more speculative requests for data from the one or more hosts, wherein a speculative request is…
Persistent switch-based storage controller
Granted: December 10, 2024
Patent Number:
12164782
Aspects of a storage device including a memory and a controller are provided. The memory includes a plurality of non-volatile memory packages coupled to the switch, with each non-volatile memory package including a plurality of non-volatile memory dies. The controller monitors a wear level of each non-volatile memory package in the plurality of non-volatile memory packages connected to the controller via the switch. The controller determines whether a wear level of a first non-volatile…
Data storage device that detects and releases bottlenecks in hardware
Granted: December 10, 2024
Patent Number:
12164775
A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a read command to read data from the memory device or a write command to write data to the memory device from a host device, determine whether a bottleneck exists in a data/control path between the host device and the memory device, wherein the bottleneck exists in a hardware module of the plurality of hardware modules, and execute a bottleneck release…
Three-dimensional memory device including an isolation-trench etch stop layer and methods for forming the same
Granted: December 3, 2024
Patent Number:
12160989
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, memory opening fill structures located within a respective one of the memory openings, and a drain-select-level isolation structure. One of the insulating layers is a composite insulating layer including an insulating-material-containing sublayer consisting essentially of an insulating material and an…
Non-volatile memory with tuning of erase process
Granted: November 26, 2024
Patent Number:
12154630
In order to achieve tight and uniform erased threshold voltage distributions in a non-volatile memory system that includes non-volatile memory cells arranged in blocks that have multiple sub-blocks and has an erase process using gate induced drain leakage (GIDL) to generate charge carriers that change threshold voltage of the memory cells, the magnitude of the GIDL is adjusted separately for the sub-blocks.
Method of forming a semiconductor device including vertical contact fingers
Granted: November 26, 2024
Patent Number:
12154860
A method of forming a semiconductor device includes forming vertical contact fingers in a substrate having side portions that are flexible. Contact fingers are formed near one or more edges of the flexible side portions of the substrate. After semiconductor dies are mounted to and electrically coupled to the substrate, the semiconductor device may be encapsulated by placing the device in a mold chase including upper and lower mold plates. The lower mold plate is sized smaller than the…
Accelerator queue in data storage device
Granted: November 26, 2024
Patent Number:
12153831
Disclosed are systems and methods for accelerating commands from accelerators in data storage devices using accelerator queues. A data storage device includes accelerator interfaces, each accelerator interface couples a controller to a respective accelerator. The device also includes a device memory comprising one or more memories and one or more sets of queues. Each set of queues corresponds to a respective memory, at least one queue is configured to queue one or more tasks associated…
Data storage device and method for scanning memory blocks
Granted: November 26, 2024
Patent Number:
12153804
Some areas (e.g., boundary wordlines) in a block of memory can be more error prone than others. Typically, errors in these areas are not detected until after the entire block is programmed. Handling such errors then can result in performance penalties and large data relocations. With the embodiments presented herein, a two-stage programming operation is provided. In the first stage, only the error-prone areas of the block are programmed, and a check is made to determine if an error…
Non-volatile memory with optimized operation sequence
Granted: November 26, 2024
Patent Number:
12153801
A non-volatile memory system separately performs a memory operation for multiple sub-blocks of a block in order from previously determined slowest sub-block of the block to a previously determined faster sub-block of the block. As a slower sub-block is more likely to fail, this order of is more likely to identify a failure earlier in the process thereby saving time and reducing potential for a disturb. In some embodiments, the proposed order of operation can be used in conjunction with a…
Non-volatile memory with adapting erase process
Granted: November 19, 2024
Patent Number:
12147695
A memory system performs an erase process for the non-volatile memory cells including performing erase verify for the non-volatile memory cells. The erase verify comprises comparing threshold voltages of the non-volatile memory cells to an erase verify reference voltage and determining whether an amount of the non-volatile memory cells having a threshold voltage greater than the erase verify reference voltage is less than an allowed bit count. During the erase process, the system…
Memory device including mixed oxide charge trapping materials and methods for forming the same
Granted: November 19, 2024
Patent Number:
12150302
A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening fill structure including a vertical semiconductor channel and a memory film. The memory film includes a tunneling dielectric layer in contact with the vertical semiconductor channel, a first vertical stack of first dielectric oxide material portions located at levels of the insulating layers and including a dielectric oxide material of a first…
Three-dimensional memory device containing bridges for enhanced structural support and methods of forming the same
Granted: November 19, 2024
Patent Number:
12148710
A three-dimensional memory device includes a first alternating stack of first word lines and first insulating layers, first memory stack structures vertically extending through the first alternating stack, a second alternating stack of second word lines and second insulating layers, second memory stack structures vertically extending through the second alternating stack, plural backside trench fill structures located between the first alternating stack and the second alternating stack,…
Early detection of programming failure for non-volatile memory
Granted: November 19, 2024
Patent Number:
12148489
An apparatus is provided that includes a block including a word line coupled to a plurality of memory cells, and a control circuit coupled to the word line. The control circuit is configured to program the plurality of memory cells by applying program pulses to the word line in a plurality of program loops, determining a first count of a number of the program loops used to complete programming a first subset of the plurality of memory cells to a first programmed state, first comparing…
Cross-point array IHOLD read margin improvement
Granted: November 19, 2024
Patent Number:
12148459
Technology for read in a cross-point memory array. Drive transistors pass read and write currents to the cross-point memory array. The read current charges a selected word line to turn on a threshold switching selector of a selected memory cell. While the threshold switching selector is on, the current (read or write) passes through the selected memory cell. The memory system applies a smaller overdrive voltage to a drive transistor when the drive transistor is passing the read current…
Ranking images in an image group
Granted: November 19, 2024
Patent Number:
12148245
Systems, methods, and data storage devices for image grouping in an end user device using trained machine learning group classifiers are described. The end user device may include an image group classifier configured to classify new image data objects using an image classification algorithm and set of machine learning parameters previously trained for a specific image group. The end user device may determine embeddings that quantify features of the target image object and use those…
Management of host file-system defragmentation in a data storage device
Granted: November 19, 2024
Patent Number:
12147704
A data storage device having a flash translation layer configured to handle file-system defragmentation in a manner that avoids, reduces, and/or optimizes physical data movement in flash memory. In an example embodiment, the memory controller maintains in a volatile memory thereof a lookaside table that supplants pertinent portions of the logical-to-physical table. Entries of the lookaside table are configured to track source and destination addresses of the host defragmentation requests…
