Management of host file-system defragmentation in a data storage device
Granted: November 19, 2024
Patent Number:
12147704
A data storage device having a flash translation layer configured to handle file-system defragmentation in a manner that avoids, reduces, and/or optimizes physical data movement in flash memory. In an example embodiment, the memory controller maintains in a volatile memory thereof a lookaside table that supplants pertinent portions of the logical-to-physical table. Entries of the lookaside table are configured to track source and destination addresses of the host defragmentation requests…
Non-volatile memory with adapting erase process
Granted: November 19, 2024
Patent Number:
12147695
A memory system performs an erase process for the non-volatile memory cells including performing erase verify for the non-volatile memory cells. The erase verify comprises comparing threshold voltages of the non-volatile memory cells to an erase verify reference voltage and determining whether an amount of the non-volatile memory cells having a threshold voltage greater than the erase verify reference voltage is less than an allowed bit count. During the erase process, the system…
Method of making ovonic threshold switch selectors using microwave annealing
Granted: November 12, 2024
Patent Number:
12144185
A method includes forming a first electrode layer over a substrate, forming an ovonic threshold switch (OTS) material layer over the first electrode layer, microwave annealing the OTS material layer, and forming a second electrode layer over the OTS material layer.
Monolithic surface mount passive component
Granted: November 12, 2024
Patent Number:
12142402
A data storage device includes a substrate including a number of contact pads and a number of passive component packages coupled to the contact pads. The data storage device further includes a memory controller coupled to the substrate, and one or more NAND die stacks coupled to the substrate and in electrical communication with the memory controller. One or more of the passive component packages include a first passive component, a second passive component electrically connected to the…
Foggy-fine drain-side select gate re-program for on-pitch semi-circle drain side select gates
Granted: November 12, 2024
Patent Number:
12142323
A memory apparatus and method of operation are provided. The apparatus includes drain-side select gate transistors for coupling to a drain-side of memory holes of memory cells and configured to retain a transistor threshold voltage. The memory holes are arranged in rows comprising strings. A control means is configured to program drain-side select gate transistors of the memory holes to an initial transistor threshold voltage using pulses increasing in magnitude by a first transistor…
Generalized verification scheme for safe metadata modification
Granted: November 12, 2024
Patent Number:
12141123
System and method of verifying validity of a metadata modification request to prevent improper metadata operations. During initialization of a volume in a storage device and once a metadata area is reserved for a metadata structure, information characterizing the metadata structure and metadata area is stored in the storage device, which may be in the form of an area legend composed of descriptors such as a magic signature, a node size, a clump size of reservation, and extent of the…
Storage system and method for improving read latency during mixed read/write operations
Granted: November 5, 2024
Patent Number:
12136462
A storage system receives a request to read data that is located in a wordline undergoing a program operation. Instead of waiting for the program operation to complete, which would increase read latency, the storage system aborts the program operation and reconstructs the data from successfully-programmed memory cells in the wordline and from data latches associated with unsuccessfully-programmed memory cells in the wordline. The reconstructed data is then sent to the host. The program…
Three-dimensional memory device with vertical word line barrier and methods for forming the same
Granted: November 5, 2024
Patent Number:
12137565
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, and memory opening fill structures located within the memory openings. Each of the electrically conductive layers includes a metallic fill material layer and a plurality of vertical tubular metallic liners laterally surrounding a respective one of the memory opening fill structures and located between…
Three-dimensional memory device with word-line etch stop liners and method of making thereof
Granted: November 5, 2024
Patent Number:
12137554
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures vertically extending through the alternating stack, etch stop plates located in the staircase region, laterally and vertically spaced apart among one another, and overlying an end portion of a respective one of the electrically conductive layers, and contact via structures located in a staircase region, vertically…
Storage-free message authenticators for error-correcting-codes
Granted: November 5, 2024
Patent Number:
12137164
Techniques for storage-free message authentication for error-correcting-codes are disclosed. A storage controller of a storage device receives a request to encode a message in a format having an error-correcting code schema that generates a parity code. A key generator generates a pseudorandom transposition of the message and the parity code as a first part of a secret key. A pseudorandom character string is determined as a second part of the secret key. The output of the pseudorandom…
Image group classifier in a user device
Granted: November 5, 2024
Patent Number:
12136293
Systems, methods, and data storage devices for image grouping in an end user device using trained machine learning group classifiers are described. The end user device may include an image group classifier configured to classify new image data objects using an image classification algorithm and set of machine learning parameters previously trained for a specific image group. The end user device may determine embeddings that quantify features of the target image object and use those…
Folding zone management optimization in storage device
Granted: November 5, 2024
Patent Number:
12135904
A data storage device for providing zone management optimization may include memories including staging memory areas (e.g., single level cells) and destination memory areas (e.g., quad-level cells). The destination memory areas may include memory regions (e.g., zones). A controller may be configured to receive data from a host system, write the data initially to the staging memory areas, receive a region full indication for a first memory region. In response to receiving the region full…
Modelling and prediction of virtual inline quality control in the production of memory devices
Granted: November 5, 2024
Patent Number:
12135542
To provide more test data during the manufacture of non-volatile memories and other integrated circuits, machine learning is used to generate virtual test values. Virtual test results are interpolated for one set of tests for devices on which the test is not performed based on correlations with other sets of tests. In one example, machine learning determines a correlation study between bad block values determined at die sort and photo-limited yield (PLY) values determined inline during…
Three-dimensional memory device with self-aligned etch stop rings for a source contact layer and method of making the same
Granted: October 29, 2024
Patent Number:
12133388
A memory device includes a lower source-level semiconductor layer, a source contact layer, an upper source-level semiconductor layer, and an alternating stack of insulating layers and electrically conductive layers, and a memory opening fill structure vertically extending through the alternating stack and down to an upper portion of the lower source-level semiconductor layer. The memory opening fill structure includes a vertical semiconductor channel, a memory film laterally surrounding…
Three-dimensional memory device with contact via structures located over support pillar structures and method of making thereof
Granted: October 29, 2024
Patent Number:
12133382
An alternating stack of insulating layers and sacrificial material layers is formed over a substrate, and support pillar structures are formed through the alternating stack. Stepped surfaces are formed by patterning the alternating stack and the support pillar structures. A retro-stepped dielectric material portion is formed over the stepped surfaces. Memory openings and memory opening fill structures are formed through the alternating stack. Electrically conductive layers are formed by…
Configurable arithmetic HW accelerator
Granted: October 29, 2024
Patent Number:
12131058
A data storage device includes a memory device and a controller coupled to the memory device. The controller includes a decoder multiplexer (mux) module, a plurality of request/response channels coupled to the decoder mux module, an arithmetic pipeline module coupled to the plurality of request/response channels, an arbiter module coupled to the plurality of request/response channels and the arithmetic pipeline module, a mux/arbiter module coupled to the arithmetic pipeline module, a…
Protocol indicator for data transfer
Granted: October 29, 2024
Patent Number:
12130766
Systems and methods are disclosed for providing an indication of the data transfer protocol that is operative during a data transfer operation between a data storage device capable of supporting a plurality of data transfer protocols and a host computer. A protocol controller of the data storage device is configured to determine a data transfer protocol based on a data cable used and to generate a selector signal used to provide the indication.
Nucleic acid sequencing by synthesis using magnetic sensor arrays
Granted: October 22, 2024
Patent Number:
12121896
Disclosed herein are apparatuses for nucleic acid sequencing, and methods of making and using such apparatuses. In some embodiments, the apparatus comprises a magnetic sensor array comprising a plurality of magnetic sensors, each of the plurality of magnetic sensors coupled to at least one address line, at least one selector element, and a fluid chamber adjacent to the magnetic sensor array, the fluid chamber having a proximal wall adjacent to the magnetic sensor array. A method of…
Data storage device and method for handling write commands in zoned storage
Granted: October 22, 2024
Patent Number:
12124377
Zoned memory typically requires write commands to be sent from a host to a data storage device in logical block address (LBA) sequential order. Instead of rejecting out-of-order write commands, the data storage device can execute those commands and internally deal with the out-of-order problem. For example, the data storage device can use a special zone logical-to-physical address table, use a temporary zone data buffer, and/or store a data's LBA in a header for later matching.
Implementation of deep neural networks for testing and quality control in the production of memory devices
Granted: October 22, 2024
Patent Number:
12124247
Techniques are presented for the application of neural networks to the fabrication of integrated circuits and electronic devices, where example are given for the fabrication of non-volatile memory circuits and the mounting of circuit components on the printed circuit board of a solid state drive (SSD). The techniques include the generation of high precision masks suitable for analyzing electron microscope images of feature of integrated circuits and of handling the training of the neural…
