System and method for memory arbitration
Granted: November 9, 2004
Patent Number:
6816947
A memory access arbitration scheme is provided where transactions to a Shared memory are stored in an arbitration queue. Prior to arbitration, the transactions are compared against the contents of cache memory, to determine which transactions will hit in cache, which will miss and which will be victims. Also prior to arbitration, the entries in the arbitration queue are grouped according to a transaction parameter, such as DRAM bank, Write to Bank, Read to Bank, etc. Arbitration is the…
Large area wide aspect ratio flat panel monitor having high resolution for high information content display
Granted: November 9, 2004
Patent Number:
6816145
A large area wide aspect ratio flat panel display having high resolution for high information content display. The present invention includes a liquid crystal flat panel display monitor having a wide aspect ratio. In one embodiment, the wide aspect ratio is substantially 1.6:1, having 1,600 pixels across the horizontal and 1,024 across the vertical. In this embodiment, the present invention is an SXGA-wide flat panel display monitor having high resolution for high information content…
Computer enclosure and method for manufacture
Granted: November 2, 2004
Patent Number:
6813151
A computer enclosure and method for manufacture include a computer housing and an outer layer, the housing having an inner surface and an outer surface, the outer layer having a first surface and a second surface, wherein the first surface of the outer layer is coupled to the outer surface of the housing and covers a substantial portion of the outer surface, and the second surface of the outer layer has a graphic design applied thereto.
Efficient memory structure simulation for sequential circuit design verification
Granted: November 2, 2004
Patent Number:
6813599
A method for efficiently simulating memory structures of a sequential circuit for design verification of the sequential circuit. The method is implemented by an computer system having a processor coupled to a memory via a bus, the memory storing computer readable code which when executed by the processor cause the computer system to perform the steps of the memory structure simulation method. The method includes accessing a netlist description of a sequential circuit, wherein the…
Scan interface chip (SIC) system and method for scan testing electronic systems
Granted: November 2, 2004
Patent Number:
6813739
A can test interface system and method provides an interface between upstream scan test devices and downstream scan test devices. In one embodiment, the present invention utilizes a scan test interface comprising a scan interface chip (SIC) that facilitates a flexibly programmable system level scan test architecture. The SIC includes a scan test interface register, a system interface, a scan test interface controller, a board interface and a selection circuit.
Swap buffer synchronization in a distributed rendering system
Granted: October 26, 2004
Patent Number:
6809733
A system and method for synchronizing image display and buffer swapping in a multiple processor-multiple display environment. In a master-slave dichotomy, one processor or system is deemed the master and the others act as slaves. The master generates signals used to control vertical retrace and buffer swapping for itself and the slaves. In addition, a synchronization signal generator is provided to synchronize a timing signal between the master and slave systems.
System, method, and computer program product for blending textures during rendering of a computer generated image using a single texture as a mask
Granted: October 26, 2004
Patent Number:
6809739
A variable number of textures are blended together using a single texture as a mask. At least four textures are received. Masks are extracted from one of the received textures and used to blend together the remaining textures. In an embodiment, N masks are extracted from a single texture and used to blend N+1 additional textures. In this embodiment, two of the N+1 textures are initially blended together in accordance with one of the N masks to form an image. Another texture of…
Programmable differential delay circuit with fine delay adjustment
Granted: October 12, 2004
Patent Number:
6803872
Circuitry that provides additional delay to early arriving signals such that all data signals arrive at a receiving latch with same path delay. The delay of a forwarded clock reference is also controlled such that the capturing clock edge will be optimally positioned near quadrature (depending on latch setup/hold requirements). The circuitry continuously adapts to data and clock path delay changes and digital filtering of phase measurements reduce errors brought on by jittering data…
Bus speed controller using switches
Granted: September 28, 2004
Patent Number:
6799238
Switches are used to serially isolate connectors for peripheral devices on a bus. Bus speed is selected based on the number of peripheral devices coupled to the bus via the connectors. Switches are used in the bus to provide selected isolation of the connectors. In one embodiment, the bus is able to operate at higher speeds when fewer connectors are on the bus. A method of configuring the bus determines how many devices are coupled to connectors on the bus. Portions of the bus not having…
Method and system for storing data at input/output (I/O) interfaces for a multiprocessor system
Granted: September 21, 2004
Patent Number:
6795900
A multiprocessor system and method includes a processing sub-system including a plurality of processors in a processor memory system. A network is operable to couple the processing sub-system to an input/output (I/O) sub-system. The I/O sub-system includes a plurality of I/O interfaces each operable to couple a peripheral device to the multiprocessor system. The I/O interfaces each include a local memory operable to store exclusive read-only copies of data from the processor memory…
Synchronization of vertical retrace for multiple participating graphics computers
Granted: September 14, 2004
Patent Number:
6791551
A system and method for synchronizing image display and buffer swapping in a multiple processor-multiple display environment. In a master-slave dichotomy, one processor or system is deemed the master and the others act as slaves. The master generates signals used to control vertical retrace and buffer swapping for itself and the slaves. In addition, a synchronization signal generator is provided to synchronize a timing signal between the master and slave systems.
Method and apparatus for accessing MMR registers distributed across a large asic
Granted: August 17, 2004
Patent Number:
6779072
A method and apparatus for accessing memory-mapped registers that are distributed across a large integrated circuit. Some embodiments provide a method for accessing memory-mapped registers that are distributed across a first integrated circuit, the first integrated circuit including a plurality of logic subset modules, wherein each of the plurality of logic subset modules includes one or more memory-mapped registers. This method includes receiving a memory-mapped register access request…
Circuit design for high-speed digital communication
Granted: August 10, 2004
Patent Number:
6775339
The present invention provides a system for efficient, high speed, high bandwidth, digital communication where transmit distances are greater than a single clock period. The digital system operates based on a system clock. Within the digital system a transmit module transmits data along with a capture clock signal to a receive module where the transmission time between the modules is greater than one period of the system clock. The capture clock operates in a known relationship to the…
Memory device storing data and directory information thereon, and method for providing the directory information and the data in the memory device
Granted: August 10, 2004
Patent Number:
6775742
A memory device and method which provide at least one memory segment. The memory segment includes at least one first portion which is configured to store data. The memory segment also includes at least one second portion associated with the first portion, and which is configured to store directory information for at least one cache line thereon.
Printed circuit board stiffener
Granted: August 3, 2004
Patent Number:
6771517
Apparatus and methods for reducing circuit board flexing is presented. The apparatus is fastened to a printed circuit board to provide rigid support for reducing bending and flexing. In one embodiment, a rigid frame is provided that is adapted to be fastened to one or more components and to be fastened to a printed circuit board. The frame is adapted to elevate the attached component from the PCB surface allowing components to be mounted on the PCB therewith. The frame is adapted to…
Multithreaded layered-code processor
Granted: July 27, 2004
Patent Number:
6769122
A multithreaded layered-code processing method includes: passing through the layered code to discover each layer of the layered code, acquiring a lock when a layer is discovered, determining whether to spawn a thread to process the discovered layer, and, if it is so determined, spawning a thread to process the discovered layer. The method may further include: releasing the lock once the new thread is either spawned or aborted, and, if spawned, proceeding with execution of the thread…
Modular fan brick and method for exchanging air in a brick-based computer system
Granted: July 20, 2004
Patent Number:
6765795
A modular computing system that includes an enclosure with a rack. A plurality of modular bricks that each include heat-generating electronic components are mounted in the rack. A fan brick that includes at least one fan is also mounted in the rack. The fan brick exchanges air between each modular brick and the fan brick to cool the electronic components in each of the modular bricks.
Exchanging messages between computer systems communicatively coupled in a computer system network
Granted: July 20, 2004
Patent Number:
6766358
A method for exchanging messages between computer systems communicatively coupled in a computer system network. A message (e.g., a read or write command) is sent from a software element of a first computer system (e.g., a client computer system) to a second computer system (e.g., a server computer system). A shared memory unit is accessible by the software element of the first computer system and a software element of the second computer system. The shared memory unit of the second…
Distributed scheduling of parallel jobs with no kernel-to-kernel communication
Granted: July 20, 2004
Patent Number:
6766515
A system and a method of scheduling a plurality of threads from a multi-threaded program. A shared arena is provided in user memory, wherein the shared arena includes a register save area for each of the plurality of threads. A processor, when allocated to the application, executes the application's user-level scheduler and selects a user-level thread from a plurality of available threads, wherein the step of selecting includes the step of reading register context associated with…
Scan interface chip (SIC) system and method for scan testing electronic systems
Granted: July 6, 2004
Patent Number:
6760876
A scan test interface system and method provides an interface between upstream scan test devices and downstream scan test devices. The scan test interface system and method receives scan test signals, facilitates flexible configuration of scan test signals and transmits scan test signals on subordinate scan test chains. A scan test interface includes a scan test interface register, a system interface, a scan test interface controller, a board interface and a selection circuit.
