Scan interface chip (SIC) system and method for scan testing electronic systems
Granted: June 22, 2004
Patent Number:
6754863
A scan test interface system and method provides an interface between upstream scan test devices and downstream scan test devices. In one embodiment, the present invention utilizes a scan test interface comprising a scan interface chip (SIC) that facilitates a flexibly programmable system level scan test architecture. The SIC includes a scan test interface register, a system interface, a scan test interface controller, a board interface and a selection circuit.
Three dimensional volumetric display input and output configurations
Granted: June 22, 2004
Patent Number:
6753847
The present invention is a system that allows a number of 3D volumetric display or output configurations, such as dome, cubical and cylindrical volumetric displays, to interact with a number of different input configurations, such as a three-dimensional position sensing system having a volume sensing field, a planar position sensing system having a digitizing tablet, and a non-planar position sensing system having a sensing grid formed on a dome. The user interacts via the input…
System and method for maintaining and recovering data consistency across multiple instances of a database
Granted: June 15, 2004
Patent Number:
6751636
The present invention is a system and method that facilitates consistency maintenance and recovery from a system or process crash with valid data. A data consistency maintenance and recovery system and method of the present invention utilizes a dual page configuration and locking process to store and track data associated with multiple indexes of a database. A primary page is utilized as the primary data storage location and a mirror page operates as copy of the primary page except…
Multiprocessor node controller circuit and method
Granted: June 15, 2004
Patent Number:
6751698
Improved method and apparatus for parallel processing. One embodiment provides a multiprocessor computer system that includes a first and second node controller, a number of processors being connected to each node controller, a memory connected to each controller, a first input/output system connected to the first node controller, and a communications network connected between the node controllers. The first node controller includes: a crossbar unit to which are connected a memory port,…
Cache line converter
Granted: June 15, 2004
Patent Number:
6751705
A method and apparatus for purging data from a middle cache level without purging the corresponding data from a lower cache level (i.e., a cache level closer to the processor using the data), and replacing the purged first data with other data of a different memory address than the purged first data, while leaving the data of the first cache line in the lower cache level. In some embodiments, in order to allow such mid-level purging, the first cache line must be in the “shared…
Device and method for storing information in memory
Granted: May 18, 2004
Patent Number:
6738885
An information capturing device (10) includes a controller (12) and a memory (14). The controller (12) partitions a memory space of the memory (14) into a plurality of memory blocks (20). The controller (12) controls the storage of received information into a first set (22) of the plurality of memory blocks (20). The controller (12) continues to store received information only in the first set (22) of the plurality of memory blocks (20) through reuse and recycle until a first triggering…
Noise estimation for coupled RC interconnects in deep submicron integrated circuits
Granted: May 4, 2004
Patent Number:
6732065
Noise estimation for coupled interconnects in deep submicron integrated circuits. One aspect of the invention is a method for interconnect coupling noise estimation. Another aspect of the invention is a computer readable medium embodying computer program code. The computer program code is configured to cause a computer to perform steps for estimating the interconnect coupling noise. The interconnect coupling noise estimation (hereafter noise estimation) includes modeling a circuit. The…
Memory daughter card apparatus, configurations, and methods
Granted: April 27, 2004
Patent Number:
6726505
New methods and configurations are provided that allow for a large memory capacity, as well as minimized interconnect distances between the memory chips and one or more processors, and the HUB chip-set. The apparatus, configurations and methods include providing a printed circuit board having one or more processor conductive portions and one or more z-axis connector conductive portions in close proximity with each other, and connecting the one or more processors on one side of a printed…
System and method for resource recovery in a distributed system
Granted: April 27, 2004
Patent Number:
6728895
A system and method for resource recovery in a distributed system uses a resource audit service to monitor the status of a client that receives a resource from a service that allocates the resource. The allocating service registers a callback with the resource audit service identifying the client. The resource audit service subsequently monitors the status of the client. When the resource audit service determines that the client has failed, the resource audit service performs the…
System and method for repairing a memory column
Granted: April 20, 2004
Patent Number:
6724669
A system for repairing a memory column includes a multiplexer operable to receive a first data bit and a second data bit. The multiplexer is operable to select one of the first data bit and the second data bit. The system also includes a control generator operable to receive a control signal indicating an error in the first data bit. The control generator is operable to generate a select signal, and the multiplexer is operable to select the second data bit in response to the select…
System and method for maintaining and recovering data consistency across multiple pages
Granted: April 13, 2004
Patent Number:
6721739
The present invention provides a system and method that facilitates data consistency maintenance between two segments of memory. A data consistency maintenance and recovery system and method of the present invention uses a dual page configuration and locking process to store and track data. A primary page is used as the primary data storage location and a mirror page operates as a copy of the primary page, except during certain stages of data manipulation operations. In one embodiment…
Method and system for using high count invalidate acknowledgements in distributed shared memory systems
Granted: April 6, 2004
Patent Number:
6718442
A multiprocessor computer system includes a method and system of handling invalidation requests to a plurality of alias processors not sharing a line of memory in a computer system. A memory directory interface unit receives an invalidation request for a shared line of memory shared in a plurality of sharing processors. A superset of processors in the computer system that includes each of the sharing processors is determined that includes at least one alias processor not sharing the…
System and method for a self-calibrating sense-amplifier strobe
Granted: March 30, 2004
Patent Number:
6714464
A system and method for self-calibration of the strobe timing of the sense-amplifiers of a RAM array. In one method example, the timing of two sense amplifiers used to read the bit-lines of the RAM array is controlled by a Delay Locked Loop circuit (DLL). The timing of a first sense-amplifier strobe is reduced until the sense amplifier fails. The second sense amplifier has adequate timing margin however and is used to actually read the RAM bit-lines. Once the RAM read fails with the…
Earnings-based time-share scheduling
Granted: March 30, 2004
Patent Number:
6714960
A precise earnings-based time-share scheduler schedules multiple jobs in a computer system by apportioning earnings, at scheduler ticks. Earnings are apportioned to jobs based on actual time a job spent in a queue requesting execution on a central processing unit (CPU) in the computer system between scheduler ticks and amounts of time jobs ran on the CPU between scheduler ticks. At the end of a time slice, a job is selected for execution on the processor based on earnings apportioned to…
Transfer attribute encoding within an address on a bus
Granted: March 23, 2004
Patent Number:
6711636
In a computer system having a plurality of modules connected by a bus, wherein the plurality of modules includes a first module and wherein the system has a word width of two or more bytes, a system and method of byte swapping bytes within a word stored in a location on the first module. An address is constructed, wherein constructing an address includes inserting address bits pointing to the location and activating an attribute bit in the address indicating whether bytes within the word…
Synthesis with automated placement information feedback
Granted: March 2, 2004
Patent Number:
6701496
A method, system, and program product for designing and verifying an electronic circuit. A circuit logic design is translated into a netlist using a synthesis tool. The synthesis tool receives inputs of placing, routing, and timing information. Timing delays in the logic design are represented in the netlist using the placing and routing information. It is determined whether a timing goal has been reached based on the timing delays. When the timing goal has not been reached, changes are…
GTL+ driver
Granted: February 3, 2004
Patent Number:
6686765
A driver operable with two power supplies, and provides, among other things, a high data communication rate, stabilized operating parameters including voltage output high, voltage output low, and on resistance, and edge rate over a wide range of variations in manufacturing process, operating voltages and temperature.
Packet switched router architecture for providing multiple simultaneous communications
Granted: January 27, 2004
Patent Number:
6683876
A novel packet switched routing architecture for establishing multiple, concurrent communications between a plurality of devices. Any number of devices are coupled to a central packet switched router via links. Due to the nature of these tightly coupled links, high data rates can be achieved between devices and the packet switched router with minimal pins. Any device can communicate to any other device via the packet switched router. The packet switched router has the capability of…
Image data compression and decompression
Granted: January 27, 2004
Patent Number:
6683979
System, method and apparatus for compressing and decompressing image data. In an embodiment, a color cell is compressed by: defining at least four luminance levels of the color cell; generating a bitmask for the color cell, the bitmask having a plurality of entries each corresponding to a respective one of the pixels, each of the entries for storing data identifying one of the luminance levels associated with a corresponding one of the pixels; calculating a first average color of pixels…
Optimize global net timing with repeater buffers
Granted: January 27, 2004
Patent Number:
6684373
A method, system, and program product for designing an electronic circuit. The electronic circuit has a source component, a sink component and a wire connecting the source and sink components. In one aspect, the wire is divided into wire segments and repeater buffers are added to connect the wire segments. The number of repeater buffers is based on the calculated delay of the global net. In another aspect, the metal routes of the wire are widened to reduce delays on a global net. In…
