Method and cache-coherence system allowing purging of mid-level cache entries without purging lower-level cache entries
Granted: January 20, 2004
Patent Number:
6681293
A method and apparatus for purging data from a middle cache level without purging the corresponding data from a lower cache level (i.e., a cache level closer to the processor using the data), and replacing the purged first data with other data of a different memory address than the purged first data, while leaving the data of the first cache line in the lower cache level. In some embodiments, in order to allow such mid-level purging, the first cache line must be in the “shared…
Method and system for clock cycle measurement and delay offset
Granted: January 20, 2004
Patent Number:
6680636
A clock edge placement circuit for implementing source synchronous communication between integrated circuit devices. The clock edge placement circuit includes a delay line having an input to receive a clock signal from an external clock source. A corresponding output is included to provide the clock signal to external logic elements. The delay line structure adapted to add a propagation delay to the input, wherein the propagation delay is sized such that the phase of the clock signal is…
System and method for reducing memory latency during read requests
Granted: January 13, 2004
Patent Number:
6678798
A processor (500) issues a read request for data. A processor interface (24) initiates a local search for the requested data and also forwards the read request to a memory directory (24) for processing. While the read request is processing, the processor interface (24) can determine if the data is available locally. If so, the data is transferred to the processor (500) for its use. The memory directory (24) processes the read request and generates a read response therefrom. The processor…
Actuatable connector system
Granted: January 6, 2004
Patent Number:
6672878
A system assembly for a computer includes a motherboard situated on a printed circuit board, and a daughterboard situated on a printed circuit board. In the system assembly the daughterboard is positioned parallel to the motherboard. The daughterboard is connected to the motherboard using a connector system. The connector system has a first portion affixed to either the motherboard or the daughterboard which includes a first capture feature and has an opening therein. A second portion…
Age-based network arbitration system and method
Granted: January 6, 2004
Patent Number:
6674720
In a multiprocessor system having a plurality of nodes connected to a network, wherein communication between the plurality of nodes is in the form of packets, a system and method of aging packets. A packet having an age value is built and transmitted through the network. The age value is increased at predetermined intervals, wherein increasing includes determining a current age of the packet and changing the interval as a function of the current age. A method of avoiding livelock and a…
Liquid crystal flat panel display with enhanced backlight brightness and specially selected light sources
Granted: December 2, 2003
Patent Number:
6657607
Brightness in the LCD is enhanced by polarization recycling using a pre-polarizing film to pre-polarize light, and a special reflector for recycling light reflected by the pre-polarizing film. In one embodiment, the pre-polarizing film comprises a layer of DBEF brightness enhancement film, and the rear reflector is made of a PTFF material. In another embodiment, the rear reflector is covered with a film comprising barium sulfate. The multiple light sources are selected such that, at any…
System, method, and computer program product for real-time shading of computer generated images
Granted: December 2, 2003
Patent Number:
6657624
A level of detail shading function is produced and stored in a computer readable memory. The level of detail shading function is produced by receiving a shading function, identifying in the shading function at least one candidate block of code for simplification, and generating, for each candidate block of code, at least one simplified block of code that can be substituted for the candidate block of code during image rendering. Candidate blocks of code and simplified blocks of code…
Data-base independent, scalable, object-oriented architecture and API for managing digital multimedia assets
Granted: November 25, 2003
Patent Number:
6654029
A system is described for providing an integrated, efficient and consistent production environment for the shared development of multimedia productions. Examples of multimedia productions include feature animation films, computerized animation films, interactive video games, interactive movies, and other types of entertainment and/or educational multimedia works. The development of such multimedia products typically involve heterogeneous and diverse forms of multimedia data. Further, the…
Multi-processor system and method of accessing data therein
Granted: November 18, 2003
Patent Number:
6651157
A multi-processor system (10) includes a plurality of processors (12). Each processor (12) has an integrated memory (16) operable to provide, receive, and store data. Each processor (12) also includes an integrated memory controller (30) in order to control read and write access to the integrated memory (16). Additionally, each processor (12) includes an integrated memory directory (18) operable to maintain a plurality of memory references to data within the integrated memory (16). The…
Method for determining the optimum locations for scan latches in a partial-scan IC built in self test system
Granted: November 18, 2003
Patent Number:
6651197
A method for determining optimum locations for scan latches using traditional fault-simulation and some additional ‘bookkeeping.’ A logic simulation is run on the IC, with single stuck-at faults injected into the circuit. The entire test set is run and records are kept of which faults are detected at every latch in the system. After the simulation run, the statistics gathered are used to indicate which system latches are the best candidates for conversion to scan latches: A…
Increasing color accuracy
Granted: November 18, 2003
Patent Number:
6650337
The present invention provides a system and method for converting color data from a higher color resolution to a lower color resolution. Color data is converted by first receiving a plurality of bits representing color data for an image. Next, a subset of pixels represented by the plurality of bits is selected. The color data for each pixel within the selected subset is then divided into least significant bits and most significant bits. Next, the least significant bits for each pixel…
Display system having floating point rasterization and floating point framebuffering
Granted: November 18, 2003
Patent Number:
6650327
A floating point rasterization and frame buffer in a computer system graphics program. The rasterization, fog, lighting, texturing, blending, and antialiasing processes operate on floating point values. In one embodiment, a 16-bit floating point format consisting of one sign bit, ten mantissa bits, and five exponent bits (s10e5), is used to optimize the range and precision afforded by the 16 available bits of information. In other embodiments, the floating point format can be defined in…
Digital tape drawing system
Granted: November 4, 2003
Patent Number:
6642927
A system that provides a bimanual user interface in which an input device is provided for each of the users hands, a left hand (LH) device and a right hand (RH) device. The input devices are used in conjunction with a large format, upright, human scale display at which the user can stand and upon which the input devices are moved. The positions of the input devices on the display are marked by displayed cursors. The system detects the position of the input devices relative to the display…
Multiprocessor system utilizing multiple links to improve point to point bandwidth
Granted: November 4, 2003
Patent Number:
6643764
A multiprocessor computer system comprises a plurality of processing element nodes and an interconnect network interconnecting the plurality of processing element nodes. An interface circuit is associated with each one of the plurality of processing element nodes. The interface circuit has a lookup table having n-number of routing entries for a given destination node. Each one of the n-number of routing entries associated with a different class of traffic. The network traffic is routed…
Curve network modeling
Granted: October 28, 2003
Patent Number:
6639592
A method of modeling complex surface models using a network of intersecting non-uniform rational B-spline curves. Topological information of the curve network and interpolating surfaces to the network of curves are automatically generated. Different levels of continuity between surface patches are enforced. Surface patches of three and four sides and positional, tangent or curvature continuity between the patches are provided. Using a constrained minimization process, arbitrary,…
Multiprocessor computer system and method for maintaining cache coherence utilizing a multi-dimensional cache coherence directory structure
Granted: October 14, 2003
Patent Number:
6633958
A cache coherence system and method for use in a multiprocessor computer system having a plurality of processor nodes, a memory and an interconnect network connecting the plurality of processor nodes to the memory. Each processor node includes one or more processors. The memory includes a plurality of lines and a cache coherence directory structure having a plurality of directory structure entries. Each of the directory structure entries is associated with one of the plurality of lines…
Method and apparatus for recording program execution in a microprocessor based integrated circuit
Granted: October 14, 2003
Patent Number:
6634011
An integrated circuit (10) includes a central processing unit (12), an instruction cache (14), a data cache, (16), and a trace recorder. The central processing unit (12) interacts with the instruction cache (14) and the data cache (16) in order to execute instructions. Profile information passed between the central processing unit (12), the instruction cache (14), and the data cache (16) not normally available for external analysis may be captured by the trace recorder (20) in response…
Memory system including guides that receive memory modules
Granted: October 7, 2003
Patent Number:
6629855
A memory system is disclosed that includes memory modules that are longer and taller than conventional prior art memory modules. Each memory module includes two roughly L-shaped openings that extend from the top surface of the memory module near each side surface of the memory module. These L-shaped openings form tabs that extend horizontally along the top surface of the memory module. A guide assembly that includes sockets and guides is adapted to receive the memory module. Rotating…
System and method for improving speed of operation of integrated circuits
Granted: September 16, 2003
Patent Number:
6621300
A system for improving the speed of operation of an integrated circuit incorporating long lines includes a first voltage operable to provide power to the circuit. The system also includes a second voltage that is less than the first voltage and a third voltage that is less than the second voltage. The system also includes a node, wherein a first status is indicated when the voltage at the node is the second voltage and a second status is indicated when the voltage at the node is the…
Upstream situated apparatus and method for providing high bandwidth data flow control to an input/output unit
Granted: September 16, 2003
Patent Number:
6622182
A method and apparatus for controlling the flow of information (e.g., graphics primitives, display data, etc.) to an input/output unit within a computer controlled graphics system. The system includes a processor having a first-in-first-out (FIFO) buffer, a separate input/output unit with its FIFO buffer, and a number of intermediate devices (with FIFO buffers) coupled between the input/output unit and the processor for moving input/output data from the processor to the input/output…
