Programmable video output format generator
Granted: October 3, 1995
Patent Number:
5455627
A programmable video output format (VOF) generator that enables a processing system to drive different video display devices with varying video format requirements. The programmable VOF generator includes a compiler that generates video formats based on user input, and a state machine that generates all video signals with requisite output format. The compiler allows the user to provide minimal information on general display parameters using a high-level language. Therefore, no…
Digital filtering for lenticular printing
Granted: August 1, 1995
Patent Number:
5438429
A method is provided which sharpens three-dimensional images by using an unsharp masking technique subsequent to interleaving and before printing.
System and method for sharpening texture imagery in computer generated interactive graphics
Granted: August 1, 1995
Patent Number:
5438654
A system and method of interactively magnifying a first texture to generate a generally unblurred high resolution display image at a particular level of detail are disclosed. The method of the present invention includes the step of extrapolating from the first texture and a second texture to generate an extrapolated frequency band. The extrapolated frequency band approximates high frequency image information contained in a texture of higher resolution than the first texture. The method…
Apparatus and method for detecting the activities of a plurality of processors on a shared bus
Granted: June 6, 1995
Patent Number:
5423008
A high performance shared-bus signal detection mechanism comprises a plurality of access event registers, an address comparator, an event masking component, and a local processor access detector. The comparator component couples to a bus providing access to a shared memory address space. The bus can be used by a single processor or shared by a plurality of processors. A processor loads the address event registers with address base and extent values and type of access notification…
Backward-compatible computer architecture with extended word size and address space
Granted: May 30, 1995
Patent Number:
5420992
A technique for extending the data word size and the virtual address space of a pre-existing architecture so that hardware for the extended architecture also supports the pre-existing architecture. Extension of the data word size from m bits to N bits entails widening the machine registers and data paths from m bits to N bits and sign-extending entities of m or fewer bits to N bits when they are loaded into registers. Some of the m-bit instructions, when operating on N-bit sign-extended…
System and Method for booting computer for operation in either of two byte-order modes
Granted: April 18, 1995
Patent Number:
5408664
A system for abstracting the byte ordering of a computer firmware from the operating system by allowing a computer to automatically change endianness under full software control. The byte ordering can be switched completely transparent to the end user during system boot. The system is comprised of hardware and software to run either byte order stand alone software or operating systems on demand.
System for obtaining correct byte addresses by XOR-ING 2 LSB bits of byte address with binary 3 to facilitate compatibility between computer architecture having different memory orders
Granted: March 14, 1995
Patent Number:
5398328
A method and apparatus for enabling a computer to run using either a Big Endian or Little Endian architecture is provided. The method and apparatus use the fact that XORing the lower two bits of a byte address in one architecture with a binary 3 converts that byte address to the equivalent byte address in the other architecture. The conversion method and apparatus is implemented in hardware by setting a bit in a status register indicating a Big Endian or Little Endian architecture in…
Apparatus and method for controlling storage of display information in a computer system
Granted: February 28, 1995
Patent Number:
5394170
A method and apparatus for controlling the storage of display information into a frame buffer is disclosed. A memory means is provided for storing information for controlling the storage of display information into the frame buffer where the memory means contains a plurality of locations each of which corresponds to and controls the storing of display information in one location of the frame buffer. A pass/fail ALU is coupled to the memory means to obtain a value for a particular pixel;…
Video timing and display ID generator
Granted: December 6, 1994
Patent Number:
5371518
An apparatus and a method of generating video timing information and display ID information wherein the video timing generator includes a memory, typically a random access memory, which stores video timing information. A control logic device couples the information from memory to a FIFO. The control device further couples the initial information from the FIFO to a second memory, typically a register, and a sequential counter. After initial loading of information in the second memory and…
Apparatus and method for generating point sample masks in a graphics display system
Granted: November 29, 1994
Patent Number:
5369739
In a computer graphics system, a method of generating a geometrically valid point sample mask corresponding to a pixel. A separate mask is generated for each edge of a polygon. These masks specify whether particular subsample points are within a half-plane defined by an edge of the polygon. This information is determined by examining the sign of vertical or horizontal distance metrics corresponding to those sample points. These separate masks are merged to form the final point sample…
Method for display rendering by determining the coverage of pixels in polygons
Granted: September 13, 1994
Patent Number:
5347618
A method for determining the coverage of a pixel, which includes determining a function of the distance from the currently sampled point to each edge of a polygon and then adding a predetermined value to the value of the function. This value is then clamped according to a function which provides an output of a predetermined value if the input to the function is not within a predetermined range and otherwise provides the value of the input if the input is within the predetermined range.…
High speed cursor generation apparatus
Granted: September 6, 1994
Patent Number:
5345252
A cursor generator for use in a computer system having a high pixel clock rate. The cursor generator includes a first memory which stores a line of the cursor for display on the display device and a second memory which stores the entire cursor. The data for the line of the cursor can be more quickly retrieved from the first memory than from the second memory, and the first memory is clocked under the control of the high pixel clock rate while the second memory is clocked at a slower…
Method for scan converting shaded triangular polygons
Granted: August 30, 1994
Patent Number:
5343558
A method for scan converting a triangular polygon where information representative of parameter values at each vertex is provided. The method includes the step of selecting an edge of the triangular polygon which is designated as a major edge and calculating parameter values for a first pixel center adjacent to the major edge, and then moving to a next pixel center adjacent to the major edge and calculating parameter values for that next pixel center adjacent to the major edge. The…
Rack and pinion retaining and release device for removable computer components
Granted: June 28, 1994
Patent Number:
5325263
A device for installing and removing a removable computer component, such as a data storage drive or computer card, into or out of a computer housing. The device features a drive sled to which the data storage drive is mounted. A stationary carrier tray is secured to the computer housing. Interlocking angled tracks on the drive sled and the carrier tray secure the two structures together. To promote easy coupling of the drive's electrical interface connectors, the front end of the drive…
Translation lookaside buffer shutdown scheme
Granted: June 28, 1994
Patent Number:
5325507
An apparatus for temporarily disabling a translation lookaside buffer in a computer system upon the occurrence of certain predefined system conditions. Such conditions may be of a first type which have been predetermined to indicate a greater risk that two or more virtual addresses stored in the TLB will simultaneously match the incoming virtual address, and/or of a second type in which access to the TLB is not needed. An example of the first type is a reference to an unmapped segment of…
Clock distribution system for an integrated circuit device
Granted: May 31, 1994
Patent Number:
5317601
Techniques for providing a number of precisely synchronized clock signals at a number of different frequencies at each of a plurality of locations on a chip. A number of synchronized clock signals are generated at an initial location on the chip, and distributed to the various locations with relative delay times that are equal to within a precision, which may be less than the ultimate precision required. A single synchronization signal is also generated at the initial location, and is…
Digital filtering for lenticular printing
Granted: May 10, 1994
Patent Number:
5311329
A method is provided which sharpens three-dimensional images by using an unsharp masking technique subsequent to interleaving and before printing.
Binary shifter
Granted: May 3, 1994
Patent Number:
5309382
A binary shifter which utilizes shifter control logic to shift a 64-bit binary word by shift amounts up to 63 bit positions using a pre-multiplexer and shifter array configuration capable of shifting up to 32 bit positions. The shifter control logic executes two cycles of shifting operations to achieve shift amounts greater than 32 bits. An improved shifter pre-multiplexer and array for shifting 64-bit binary words by up to 32 bit positions in one cycle is disclosed. The improved shifter…
Z-subdivision for improved texture mapping
Granted: April 26, 1994
Patent Number:
5307450
A graphical display system and a method for Z-subdivision of polygons into quadrilaterals and triangles whose vertices are arranged between two adjacent Z planes. This slicing allows both atmospheric and texture parameters to be interpolated linearly with minimal error within each quadrilateral or triangle slice. Object data from a host computer is processed by four pipelined graphics subsystems before being displayed on a display screen. Each object is decomposed into a set of…
File alteration monitor for computer operating and file management system
Granted: February 15, 1994
Patent Number:
5287504
A server to which clients subscribe for on-the fly notice of alterations to files and directories in a computer having an operating and file management system. The server also provides status of the execution state of executable code, alteration detection for multiple requests from multiple clients, and tracks files and directories on a user's local station. In addition, the server monitors network-mounted files on remote computers even though events are only generated for local activity…
