PROGRAMMABLE READ PREAMBLE
Granted: July 21, 2011
Application Number:
20110179215
The subject systems and/or methods relate to a high speed memory device that enables a preamble pattern to be updated after manufacture. A high speed memory device can include a FLASH module and a RAM module. The FLASH module can include an initial preamble pattern, wherein the initial preamble pattern is loaded during a power-up of the high speed memory. The RAM module can include a default preamble pattern, wherein the default preamble pattern is loaded after the power-up of the high…
FIELD PROGRAMMABLE REDUNDANT MEMORY FOR ELECTRONIC DEVICES
Granted: July 21, 2011
Application Number:
20110179319
An electronic device is provided including an input/output (I/O) interface, a plurality of memory elements, a controller coupled to the I/O interface and the plurality of memory elements. In the device, the controller configured for operating the plurality of memory elements during a normal operating mode of the electronic device, where responsive to receiving a command for replacing a selected memory sector in the electronic device during the normal operating mode, the controller is…
HTO OFFSET AND BL TRENCH PROCESS FOR MEMORY DEVICE TO IMPROVE DEVICE PERFORMANCE
Granted: July 14, 2011
Application Number:
20110169069
Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line…
MEMORY DEVICE
Granted: July 7, 2011
Application Number:
20110164452
Systems (100) and methods (600) for reading data from a memory device (106). The methods involve (606) receiving first read request signals (118, 120, 122, 126, 128) for first data stored in the memory device. In response to the first read request signals, (608) retrieving a first page of data from a cell array (268) of the memory device. The methods also involve (616) receiving second read request signals for second data stored in the memory device. (618) Next, a determination is made…
METHOD FOR FORMING NARROW STRUCTURES IN A SEMICONDUCTOR DEVICE
Granted: June 30, 2011
Application Number:
20110156130
A method of forming multiple conductive structures in a semiconductor device includes forming spacers adjacent side surfaces of a mask, where the mask and the spacers are formed on a conductive layer. The method also includes etching at least one trench in a portion of the conductive layer not covered by the spacers or the mask. The method may further include depositing a material over the semiconductor device, removing the mask and etching the conductive layer to remove portions of the…
HIGH READ SPEED ELECTRONIC MEMORY WITH SERIAL ARRAY TRANSISTORS
Granted: June 23, 2011
Application Number:
20110149630
Providing a serial array semiconductor architecture achieving fast program, erase and read times is disclosed herein. By way of example, a memory architecture can comprise a serial array of semiconductors coupled to a metal bitline of an electronic memory device at one end of the array, and a gate of a pass transistor at an opposite end of the array. Furthermore, a second metal bitline is coupled to a drain of the pass transistor. A sensing circuit that measures current or voltage at the…
VARIABLE READ LATENCY ON A SERIAL MEMORY BUS
Granted: June 23, 2011
Application Number:
20110153900
Systems and/or methods are provided that facilitate employing a variable read latency on a serial memory bus. In an aspect, a memory can utilize an undefined amount of time to obtain data from a memory array and prepare the data for transfer on the serial memory bus. The serial memory bus can be driven to a defined state. When data is ready for transfer, the memory can assert a start bit on the serial memory bus to notify a host prior to initiating the data transfer.
READ PREAMBLE FOR DATA CAPTURE OPTIMIZATION
Granted: June 23, 2011
Application Number:
20110153915
Systems and/or methods are provided that facilitate data capture optimization for devices accessing memories via a bus. In an aspect, a memory can output a read preamble prior to pushing data onto a bus. The read preamble can be a known sequence of one or more bits. A host device accessing the memory via the bus can analyze the read preamble and, particularly, timing characteristics of the read preamble. The timing characteristics can be utilized to identify an optimal capture point…
PROCESSES FOR FORMING ELECTRONIC DEVICES INCLUDING POLISHING METAL-CONTAINING LAYERS
Granted: June 9, 2011
Application Number:
20110136268
A process of forming an electronic device can include providing a workpiece. The workpiece can include a substrate, an interlevel dielectric overlying the substrate, a refractory-metal-containing layer over the interlevel dielectric, and a first metal-containing layer over the refractory-metal-containing layer. The first metal-containing layer can include a metal element other than a refractory metal element. The process further includes polishing the first metal-containing layer and the…
LOCAL INTERCONNECT HAVING INCREASED MISALIGNMENT TOLERANCE
Granted: June 2, 2011
Application Number:
20110129976
A method is provided for forming an interconnect in a semiconductor memory device. The method includes forming a pair of source select transistors on a substrate. A source region is formed in the substrate between the pair of source select transistors. A first inter-layer dielectric is formed between the pair of source select transistors. A mask layer is deposited over the pair of source select transistors and the inter-layer dielectric, where the mask layer defines a local interconnect…
METHOD AND APPARATUS FOR PERFORMING SEMICONDUCTOR MEMORY OPERATIONS
Granted: May 26, 2011
Application Number:
20110122708
A semiconductor memory device and a method for performing a memory operation in the semiconductor memory device are provided. The semiconductor memory device includes a plurality of predetermined memory arrays, a bitline decoder, and a controller. The controller provides the memory operation signal to the bitline decoder and, after precharging bitlines of the plurality of predetermined memory arrays, performs the memory operation on selected memory cells in the one or more of the…
SPLIT CHARGE STORAGE NODE OUTER SPACER PROCESS
Granted: April 28, 2011
Application Number:
20110095355
Memory cells containing two split sub-lithographic charge storage nodes on a semiconductor substrate and methods for making the memory cells are provided. The methods can involve forming two split sub-lithographic charge storage nodes by using spacer formation techniques. By removing an exposed portion of a fist poly layer between sloping side surfaces or outer surfaces of spacers while leaving portions of the first poly layer protected by the spacers, the method can provide two split…
LOCAL INTERCONNECT HAVING INCREASED MISALIGNMENT TOLERANCE
Granted: April 14, 2011
Application Number:
20110084330
A method is provided for forming an interconnect in a semiconductor memory device. The method includes forming a pair of source select transistors on a substrate. A source region is formed in the substrate between the pair of source select transistors. A first inter-layer dielectric is formed between the pair of source select transistors. A mask layer is deposited over the pair of source select transistors and the inter-layer dielectric, where the mask layer defines a local interconnect…
PARALLEL BITLINE NONVOLATILE MEMORY EMPLOYING CHANNEL-BASED PROCESSING TECHNOLOGY
Granted: April 7, 2011
Application Number:
20110080792
Providing for a new combination of non-volatile memory architecture and memory processing technology is described herein. By way of example, disclosed is a parallel bitline semiconductor architecture coupled with a channel-based processing technology. The channel based processing technology provides fast program/erase times, relatively high density and good scalability. Furthermore, the parallel bitline architecture enables very fast read times comparable with drain-based tunneling…
MEMORY DEVICE
Granted: March 3, 2011
Application Number:
20110051529
Systems and methods for reading data from or writing data to a memory device. The methods involve receiving a first pulse signal having a first pulse frequency at the memory device. The methods also involve generating, at the memory device, a second pulse signal using the first pulse signal. The second pulse signal is a compliment of the first pulse signal. The second pulse signal has a second pulse frequency that is equal to the first frequency. The first pulse signal is used to control…
SYSTEM AND METHOD FOR IMPROVING MESA WIDTH IN A SEMICONDUCTOR DEVICE
Granted: February 17, 2011
Application Number:
20110037115
A method for forming a memory device is provided. A nitride layer is formed over a substrate. The nitride layer and the substrate are etched to form a trench. The nitride layer is trimmed on opposite sides of the trench to widen the trench within the nitride layer. The trench is filled with an oxide material. The nitride layer is stripped from the memory device, forming a mesa above the trench.
PLANARIZATION METHOD USING HYBRID OXIDE AND POLYSILICON CMP
Granted: January 13, 2011
Application Number:
20110008966
A method of planarizing a semiconductor device is provided. The semiconductor device includes a substrate, first and second components provided on the surface of the substrate, and a first material provided between and above the first and second components. The first component has a height greater than a height of the second component. The method includes performing a first polishing step on the semiconductor device to remove the first material above a top surface of the first component,…
METHOD FOR FORMING BIT LINES FOR SEMICONDUCTOR DEVICES
Granted: December 30, 2010
Application Number:
20100330762
A memory device includes a number of memory cells and a number of bit lines. Each of the bit lines includes a first region having a first width and a first depth and a second region having a second width and a second depth, where the first width is less than the second width. The first region may include an n-type impurity and the second region may include a p-type impurity,
MEMORY EMPLOYING INDEPENDENT DYNAMIC REFERENCE AREAS
Granted: December 30, 2010
Application Number:
20100329003
A memory that employs separate Dref areas that are independently accessed to provide a threshold voltage reference signal. The memory includes the separate Dref areas, a data area positioned between the Dref areas, one or more sense amplifiers, and a switch component. The switch component is arranged to receive addressing data and to independently couple one of the separate Dref areas to the sense amplifiers based, at least in part, on a physical proximity of individual memory cells…
ELECTRONIC DEVICE HAVING A MOLDING COMPOUND INCLUDING A COMPOSITE MATERIAL
Granted: December 30, 2010
Application Number:
20100327417
An electronic device includes a packaged integrated circuit having an integrated circuit die having an active surface, and a molding compound overlaying the active surface of the integrated circuit die. In a particular embodiment, the packaged integrated circuit includes at least approximately five weight percent (5 wt %) zinc relative to the molding compound. In another embodiment, the packaged integrated circuit includes approximately 0.3 ?mol/cm2 of zinc in an area parallel to the…
