METHOD FOR FORMING BIT LINES FOR SEMICONDUCTOR DEVICES
Granted: December 30, 2010
Application Number:
20100330762
A memory device includes a number of memory cells and a number of bit lines. Each of the bit lines includes a first region having a first width and a first depth and a second region having a second width and a second depth, where the first width is less than the second width. The first region may include an n-type impurity and the second region may include a p-type impurity,
SYSTEM AND METHOD FOR REDUCING PROCESS-INDUCED CHARGING
Granted: December 16, 2010
Application Number:
20100314753
A semiconductor device includes a substrate, a memory cell formed on the substrate, and a contact to the substrate. The contact is formed in an area away from the memory cell and functions to raise the potential of the substrate.
RADIATION DETECTING DEVICE AND METHOD OF OPERATING
Granted: November 25, 2010
Application Number:
20100294946
A method of operating a radiation-detecting device includes charging a first charge storage region of a charge storage structure to place a first charge value at the first charge storage region, and charging a second charge storage region of the charge storage structure to place a second charge value at the second charge storage region. The method further includes conducting a first read operation to determine a change in the first charge value at the first charge storage region at a…
Electronic Device Including a Gate Electrode Having Portions with Different Conductivity Types
Granted: November 18, 2010
Application Number:
20100289072
An electronic device can include a gate electrode having different portions with different conductivity types. In an embodiment, a process of forming the electronic device can include forming a semiconductor layer over a substrate, wherein the semiconductor layer has a particular conductivity type. The process can also include selectively doping a region of the semiconductor layer to form a first doped region having an opposite conductivity type. The process can further include…
DIRECT POINTER ACCESS AND XIP REDIRECTOR FOR EMULATION OF MEMORY-MAPPED DEVICES
Granted: November 4, 2010
Application Number:
20100280817
A system, apparatus and method for emulating memory-mapped devices in the development of software where a device is mapped to protected memory space. When an instruction causing an attempted read or write to the protected space occurs, an exception or interrupt occurs, the instruction is analyzed and converted into a function call. The function call is sent to a device simulator for execution. The results of the function call are then used to update the registers of the processor and…
REPLACING RESET PIN IN BUSES WHILE GUARANTEEING SYSTEM RECOVERY
Granted: November 4, 2010
Application Number:
20100281293
Systems and methods are disclosed that replace a separate reset pin in a bus with a reset command that guarantees a system recovery. The system comprises a host component circuitry residing on a first chip and a client component circuitry residing on a second, different chip. A bus connects the host component circuitry to the client component circuitry. The host component circuitry is configured to transfer an initial client value associated with a client component time period to the…
USE OF A POLYMER SPACER AND SI TRENCH IN A BITLINE JUNCTION OF A FLASH MEMORY CELL TO IMPROVE TPD CHARACTERISTICS
Granted: October 21, 2010
Application Number:
20100264480
Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains one or more charge storage nodes, a first poly gate, a pair of first bit lines, and a pair of second bit lines. The second bit line can be formed at a higher energy…
GATE TRIM PROCESS USING EITHER WET ETCH OR DRY ETCH APPRAOCH TO TARGET CD FOR SELECTED TRANSISTORS
Granted: October 21, 2010
Application Number:
20100264519
Disclosed are methods and devices for targeting CD of selected transistors in a semiconductor device. Varying CD is done by forming hard mask lines in a hard mask layer that have varying amounts of spacer material associated therewith. Hard mask lines corresponding to selected transistors are either left covered or uncovered by a resist applied over the hard mask layer. Then, spacer material is selectively removed from the hard mask lines to vary the width of hard mask lines and…
STRAPPING CONTACT FOR CHARGE PROTECTION
Granted: September 23, 2010
Application Number:
20100240210
A semiconductor device includes a substrate and a memory cell formed on the substrate. The memory cell includes a word line. The semiconductor device also includes a protection area formed in the substrate, a conductive structure configured to extend the word line to the protection area, and a contact configured to short the word line and the protection area.
METHOD FOR CONTAINING A SILICIDED GATE WITHIN A SIDEWALL SPACER IN INTEGRATED CIRCUIT TECHNOLOGY
Granted: September 2, 2010
Application Number:
20100219486
A method of forming an integrated circuit includes providing a semiconductor substrate and forming a gate over the semiconductor substrate. A gate sidewall spacer is formed around the gate and a resist is deposited on the gate sidewall spacer with the gate sidewall spacer and the gate exposed. A portion of the gate within the gate sidewall spacer is removed and a gate silicide is formed within the curved gate sidewall spacer. A dielectric layer is formed over the gate silicide and a…
ADJACENT WORDLINE DISTURB REDUCTION USING BORON/INDIUM IMPLANT
Granted: August 26, 2010
Application Number:
20100213535
Semiconductor devices having reduced parasitic current and methods of malting the semiconductor devices are provided. Further provided are memory devices having reduced adjacent wordline disturb. The memory devices contain wordlines formed over a semiconductor substrate, wherein at least one wordline space is formed between the wordlines. Adjacent wordline disturb is reduced by implanting one or more of indium, boron, and a combination of boron and indium in the surface of the at least…
METHOD AND DEVICE EMPLOYING POLYSILICON SCALING
Granted: August 19, 2010
Application Number:
20100207191
A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral…
PIN DIODE DEVICE AND ARCHITECTURE
Granted: August 19, 2010
Application Number:
20100208517
A memory architecture that employs one or more semiconductor PIN diodes is provided. The memory employs a substrate that includes a buried bit/word line and a PIN diode. The PIN diode includes a non-intrinsic semiconductor region, a portion of the bit/word line, and an intrinsic semiconductor region positioned between the non-intrinsic region and the portion of the bit/word line.
SELECTIVE APPLICATION OF WORD LINE BIAS TO MINIMIZE FRINGE EFFECTS IN ELECTROMAGNETIC FIELDS DURING ERASE OF NONVOLATILE MEMORY
Granted: August 19, 2010
Application Number:
20100208527
A memory device comprising an optimization component that facilitates erasing memory cells in a substantially homogeneous electromagnetic field and methods that facilitate erasing memory cells in a substantially homogeneous electromagnetic field are presented. The optimization component facilitates selecting a subset of memory cells to be erased at the same time, such that a memory cell in the subset of memory cells has two neighbor memory cells adjacent thereto that are in the subset of…
Self-aligned double patterning for memory and other microelectronic devices
Granted: July 29, 2010
Application Number:
20100187596
A method for transferring a pattern to one or more microelectronic layers. A first mask layer, having a patterned feature, and a second mask layer, having another patterned feature, are formed. The first mask layer and the second mask layer are at least partially covered with a film, and openings are formed in the film by removing the other patterned feature of the second mask layer. A pattern of a microelectronic layer is then defined by patterning the patterned feature of the first…
READ MODE FOR FLASH MEMORY
Granted: July 15, 2010
Application Number:
20100177568
A method for reading a nonvolatile memory array including an array of memory cells, each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region, includes receiving, at an address register, a read command including an address for a memory cell in the array of memory cells and an indication regarding whether the read command is a full page read command or a partial page read command. A starting address for a page including the…
RADIATION-DETECTING STRUCTURES
Granted: June 24, 2010
Application Number:
20100155611
A mobile device including a housing, a wireless signal transceiver contained within the housing, and a radiation-detecting structure comprising a charge storage structure contained within the housing to detect radiation.
RADIATION DETECTING ELECTRONIC DEVICE AND METHODS OF OPERATING
Granted: June 24, 2010
Application Number:
20100155618
A method of operating an electronic device including determining an initial charge level at a non-volatile charge storage structure of a radiation-sensitive device including a radiation-reactive material and determining if a first radiation event has occurred based upon the non-volatile charge storage device having a different charge level than the initial charge level. The method further includes identifying the first radiation event as associated with either a first type of radiation…
HTO OFFSET SPACERS AND DIP OFF PROCESS TO DEFINE JUNCTION
Granted: June 24, 2010
Application Number:
20100155785
Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The memory cell contains a pair of first bit lines and a pair of second bit lines. The first and second bit lines can be formed by an implant process using first and second spacers that have different lateral…
HTO OFFSET AND BL TRENCH PROCESS FOR MEMORY DEVICE TO IMPROVE DEVICE PERFORMANCE
Granted: June 24, 2010
Application Number:
20100155816
Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line…
